USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 40

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

MMU Free Pages Register
MMU Free Pages bits, and a global NAK_ALLRX (this can only NACK OUT and Bulk packets) control bit for the
firmware to view the real time status of the 32 page allocation bits. This allows the MCU to set NAK_ALLRX which
would inhibit the SIE from asking the SIEDMA to allocate packets, MCU checks how many pages are left, issue an
allocate if enough are free, and then release the SIE/SIEDMA. For the current design, the number of free pages
would range from 0x00 to 0x1F (32) pages left unallocated.
The indication of pages free may be invalid during an allocation or deallocation.
Notes:
16 BYTE DEEP TX COMPLETION FIFO REGISTER
SMSC DS – USB97C100
Firmware can set a NAK_ALLRX bit to inhibit the SIE from asking the SIEDMA to allocate any pages while the
MCU is observing the page free bits.
This register is used to indicate how many pages are left in many situations, including after an RX_OVRN,
before a multi-packet allocation, etc. This eliminates the possibility of a failed allocation, simplifying software
without adding additional hardware to abort an allocation.
[4:0]
BIT
[5:0]
BIT
7
6
5
7
6
(0x7F56 - RESET=0x20)
(0x7F57 - RESET=0x80)
PAGS_FREE
PAGS_FREE
NAK_ALLRX
CTX_EMTY
CTX_FULL
Reserved
TX_MGMT
CTX_FIFO
Reserved
NAME
NAME
R/W
R/W
R
0
R/W
R
R
R
R
Table 67 - TX Management Register 2
Table 66 - Pages Free In The MMU
0 = Normal Operation (Default)
1 = NACK all RX packets
Reserved
NACK All received packets
These bits indicate the number of free pages in the MMU.
Completed TX FIFO empty status
0 = Has one or more TX packet
1 = Empty
Completed TX FIFO full status
0 = Not FULL
1 = FULL
Reserved
This is the data port for the 16 deep TX completion FIFO. This
FIFO is automatically updated by hardware with the last
successfully completed transmit packet. It is the responsibility of
software to ensure that this FIFO never overflows and/or becomes
full.
Page 40
PAGES FREE IN THE MMU
TX Management Register
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001