USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 44

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

SMSC DS – USB97C100
[7:1]
BIT
BIT
7
6
5
4
3
2
1
0
0
(0x7F67 - RESET=0x00)
(0x7F63 - RESET=0x55)
EP15TX_EMPTY
EP14TX_EMPTY
EP13TX_EMPTY
EP12TX_EMPTY
EP15TX_FULL
EP14TX_FULL
EP13TX_FULL
EP12TX_FULL
MEM_DALL
Reserved
TXSTAT_D
TX_MGMT
NAME
NAME
Table 73 - Transmit FIFO Status Register D
Table 74 - TX Management Register 1
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
Reserved
0 = Auto
1 = Manual deallocation, but the TX FIFO Pop is still
automatic.
This control bit selects between Auto and Manual memory
pages deallocation. This bit should be statically set at the
start of operation, and can not be changed during or if
about to transmit. This bit defaults to “0” for normal
operation. When set, the MCU handles freeing up the
memory pages.
Endpoint 15 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 14 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 13 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 12 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Memory deallocate Mode
Page 44
TRANSMIT FIFO STATUS REGISTER D
TX Management Register 1
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001