USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 28

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

Notes:
SMSC DS – USB97C100
Each bit in this register reflects the current value of the corresponding bit in the 8237 CH_STAT status register.
The 8237 clears bits 3..0 in the CH_STAT status register when the 8051 reads it through the ISA Bus I/O
Window.
Reading the BUS_STAT register does not clear or otherwise affect the BUS_STAT register.
The ISADMA bit in ISR_0 is latched high whenever any bit in BUS_STAT that is enabled in BUS_MASK
transitions from low to high.
This register is intended (1) to provide a view into the status of the 8237 without having to assume control of the
ISA bus during DMA transfers, and (2) to provide a means for generating the ISADMA interrupt in ISR_0 which
indicates that a DMA transfer has completed and that the 8051 should take control of the bus and setup the
8237 for its next transfer. Bits 7-4 can be used to generate additional interrupt requests from the DREQ pins, or
simply to monitor channel request status by masking them.
BIT
7
6
5
4
3
2
1
0
(0x7F73 - RESET=0xXX)
CH3RQ
CH2RQ
CH1RQ
CH0RQ
CH3TC
CH2TC
CH1TC
CH0TC
BUS_STAT
NAME
R/W
R
R
R
R
R
R
R
R
Table 34 - ISA Bus Status Register
Channel 3 DMA Request
0 = No Request Pending
1 = Request Pending
Channel 2 DMA Request
0 = No Request Pending
1 = Request Pending
Channel 1 DMA Request
0 = No Request Pending
1 = Request Pending
Channel 0 DMA Request
0 = No Request Pending
1 = Request Pending
Channel 3 Terminal Count Reached
0 = No
1 = Yes
Channel 2 Terminal Count Reached
0 = No
1 = Yes
Channel 1 Terminal Count Reached
0 = No
1 = Yes
Channel 0 Terminal Count Reached
0 = No
1 = Yes
Page 28
ISA BUS STATUS REGISTER
DESCRIPTION
Rev. 01/03/2001