ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 10

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Pin
SBTS
IRQ
FLAG
TIMEXP
HBR
HBG
CS
REDY (O/D)
DMAR1
DMAR2
DMAG1
DMAG2
BR
ID
RPBA
CPA (O/D)
DTx
DRx
TCLKx
RCLKx
ADSP-21061/ADSP-21061L
2-0
6-1
2-0
3-0
Type
I/S
I/A
I/O/A
O
I/A
I/O
I/A
O
I/A
I/A
O/T
O/T
I/O/S
I
I/S
I/O
O
I
I/O
I/O
Function
Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061
attempts to access external memory while SBTS is asserted, the processor will halt and the memory
access will not be completed until SBTS is deasserted. SBTS should only be used to recover from
PAGE faults or host processor/ADSP-21061 deadlock.
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21061’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master
will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address,
data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus
requests (BR
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
control of the external bus. HBG is asserted (held low) by the ADSP-21061 until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-21061 bus master and is monitored by all others.
Chip Select. Asserted by host processor to select the ADSP-21061.
Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-
nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 7).
DMA Request 2 (DMA Channel 6).
DMA Grant 1 (DMA Channel 7).
DMA Grant 2 (DMA Channel 6).
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061s to arbitrate for bus master-
ship. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins
should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by ADSP-
21061. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or only changed at
reset.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-
figuration selection which must be set to the same value on every ADSP-21061. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave
to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain
output that is connected to all ADSP-2106Ls in the system. The CPA pin has an internal 5 kΩ pull-up
resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
6-1
) in a multiprocessing system.
2-0
inputs) and