ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 23

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes (see Memory Read—
Bus Master and Memory Write—Bus Master).
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of Wait states specified in WAIT register) × t
NOTES
1
2
3
4
SSDATI
SSDATI
HSDATI
DAAK
SACKC
HACK
DADRO
HADRO
DPGC
DRDO
DWRO
DWRO
DRWL
SDDATO
DATTR
DADCCK
ADRCK
ADRCKH
ADRCKL
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
ACK Delay/Setup: User must meet t
Data Hold: User must meet t
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
same name.
of ACK (High).
times given capacitive and dc loads.
(50 MHz) WR High Delay after CLKIN,
(50 MHz) Data Setup before CLKIN,
Data Setup before CLKIN
Data Hold after CLKIN
ACK Delay after Address, MSx,
SW, BMS
ACK Setup before CLKIN
ACK Hold after CLKIN
Address, MSx, BMS, SW Delay
after CLKIN
Address, MSx, BMS, SW Hold
after CLKIN
PAGE Delay after CLKIN
RD High Delay after CLKIN
WR High Delay after CLKIN
t
RD/WR Low Delay after CLKIN
Data Delay after CLKIN
Data Disable after CLKIN
ADRCLK Delay after CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
t
CK
CK
= 20 ns
= 20 ns
HDA
2, 3
1
1
2
or t
DAAK
HDRH
or t
or synchronous specification t
DSAK
4
2
or synchronous specification t
CK
Min
2 + DT/8
1.5 + DT/8
3.5 – DT/8
6.5 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
–1.5 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
t
(t
(t
CK
.
CK
CK
/2 – 2)
/2 – 2)
ADSP-21061 (5 V)
HDATI
. See System Hold Time Calculation under Test Conditions for the calculation of hold
SACKC
CK
12 + DT/4
Max
15 + 7 DT/8 + W
6.5 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
4 – 3DT/16
19 + 5DT/16
7 – DT/8
10 + DT/8
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21061 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
< 25 ns. For all other devices, use the preceding timing specification of the
for deassertion of ACK (Low), all three specifications must be met for assertion
ADSP-21061/ADSP-21061L
Min
2 + DT/8
3.5 – DT/8
6.5 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
t
(t
(t
CK
CK
CK
/2 – 2)
/2 – 2)
ADSP-21061L (3.3 V)
Max
15 + 7 DT/8 + W
6.5 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
12 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns