ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is
the bus master accessing external memory space. These switching
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
HI = t
H = t
NOTES
1
2
3
4
DAD
DRLD
HDA
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
SADADC
Data Delay/Setup: User must meet t
The falling edge of MSx, SW, and BMS is referenced.
Data Hold: User must meet t
ACK Delay/Setup: User must meet t
times given capacitive and dc loads.
tion of ACK (High).
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Hold from Address, Selects
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address, Selects Hold after RD High
Address, Selects to RD Low
RD Pulsewidth
RD High to WR, RD, DMAGx Low
Address, Selects Setup before
ADRCLK High
WR, DMAG
ADDRESS
MSx, SW
ADRCLK
DATA
(OUT)
BMS
ACK
RD
2
HDA
or t
1
DAD
DAAK
HDRH
t
SADADC
3
4
or t
2
or t
or synchronous specification t
t
DRLD
DARL
DSAK
3
t
2, 4
DAAK
or synchronous specification t
1, 2
or synchronous specification t
CK
Min
0.5
2.0
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + DT/4
.
t
t
DSAK
DAD
ADSP-21061 (5 V)
t
DRLD
HSDATI
. See System Hold Time Calculation under Test Conditions for the calculation of hold
SSDATI
SACKC
Max
18 + DT + W
12 + 5DT/8 + W
15 + 7DT/8 + W
8 + DT/2 + W
t
.
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write—Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
RW
for deassertion of ACK (Low), all three specifications must be met for asser-
ADSP-21061/ADSP-21061L
Min
0.5
2.0
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + DT/4
ADSP-21061L (3.3 V)
t
HDRH
t
t
HDA
DRHA
t
RWR
Max
18 + DT + W
12 + 5DT/8 + W
15 + 7DT/8 + W
8 + DT/2 + W
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns