ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 22

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is
the bus master accessing external memory space. These switching
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
I = t
NOTES
1
2
3
ADSP-21061/ADSP-21061L
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
DDWR
WDE
SADADC
ACK Delay/Setup: User must meet t
tion of ACK (High)
The falling edge of MSx, SW, and BMS is referenced.
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
CK
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulsewidth
Data Setup before WR High
Address Hold after WR Deasserted
Data Disable after WR Deasserted
WR High to WR, RD, DMAGx Low
Data Disable before WR or RD Low
WR Low to Data Enabled
Address, Selects to ADRCLK High
ADDRESS
RD, DMAG
MSx , SW
ADRCLK
DATA
(OUT)
BMS
ACK
WR
DAAK
t
SADADC
1
or t
2
t
DAWL
DSAK
1, 2
3
2
2
or synchronous specification t
t
DAAK
CK
Min
17 + 15DT/16 + W
3 + 3DT/8
13 + 9DT/16 + W
7 + DT/2 + W
1 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
.
t
DSAK
t
WDE
ADSP-21061 (5 V)
t
DAWH
SACKC
Max
15 + 7DT/8 + W
8 + DT/2 + W
6 + DT/16 + H
t
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write—Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
WW
for deassertion of ACK (Low), all three specifications must be met for asser-
t
DDWH
Min
17 + 15DT/16 + W
3 + 3DT/8
13 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
ADSP-21061L (3.3 V)
t
DATRWH
t
DWHA
t
Max
15 + 7DT/8 + W
8 + DT/2 + W
6 + DT/16 + H
WWR
t
DDWR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns