ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
ADSP-21061/ADSP-21061L
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
ADCEN
ADCTR
MTRHBG
MENHBG
Strobes = RD, WR, MSx, SW, PAGE, DMAG, BMS.
In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
SBTS Setup before CLKIN
SBTS Hold before CLKIN
Address/Select Enable after CLKIN
Strobes Enable after CLKIN
HBG Enable after CLKIN
Address/Select Disable after CLKIN
Strobes Disable after CLKIN
HBG Disable after CLKIN
Data Enable after CLKIN
Data Disable after CLKIN
ACK Enable after CLKIN
ACK Disable after CLKIN
ADRCLK Enable after CLKIN
ADRCLK Disable after CLKIN
Memory Interface Disable before HBG Low
Memory Interface Enable after HBG High
2
2
2
2
1
1
3
3
Min
12 + DT/2
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0 + DT/8
19 + DT
ADSP-21061 (5 V)
Max
6 + DT/2
0 – DT/4
1.5 – DT/4
2 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
Min
12 + DT/2
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0 + DT/8
19 + DT
ADSP-21061L (3.3 V)
Max
6 + DT/2
0 – DT/4
1.5 – DT/4
2 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns