ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 19

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Parameter
Clock Input
Timing Requirements:
t
t
t
t
Parameter
Clock Input
Timing Requirements:
t
t
t
t
Parameter
Reset
Timing Requirements:
t
t
NOTES
1
2
Parameter
Interrupts
Timing Requirements:
t
t
t
NOTES
1
2
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
Only required for IRQx recognition in the following cycle.
Applies only if t
CK
CKL
CKH
CKRF
CK
CKL
CKH
CKRF
WRST
SRST
low, assuming stable V
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
SIR
HIR
IPW
SIR
and t
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
RESET Pulsewidth Low
RESET Setup before CLKIN High
IRQ2-0 Setup before CLKIN High
IRQ2-0 Hold before CLKIN High
IRQ2-0 Pulsewidth
DD
HIR
and CLKIN (not including start-up time of external clock oscillator).
requirements are not met.
RESET
CLKIN
2
CLKIN
1
1
2
1
Min
30
7
5
33 MHz
t
CKH
Min
4t
14 + DT/2
Min
18 + 3DT/4
2 + t
ADSP-21061 (5 V)
CK
ADSP-21061 (5 V)
Min
25
7
5
t
Max
100
3
WRST
CK
40 MHz
t
CK
t
Max
t
Max
12 + 3DT/4
ADSP-21061 (5 V)
CKL
CK
Max
100
3
Min
25
7
5
ADSP-21061L (3.3 V)
40 MHz
ADSP-21061/ADSP-21061L
t
SRST
ADSP-21061L (3.3 V)
Min
4t
14 + DT/2
Min
18 + 3DT/4
2 + t
Max
100
3
ADSP-21061L (3.3 V)
CK
CK
Min
7
22.5
5
Min
20
7
5
44 MHz
Max
t
Max
12 + 3DT/4
50 MHz
CK
Max
100
3
Max
100
3
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
Unit
ns
ns
ns