ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 25

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
NOTES
1
2
3
4
SADRI
HADRI
SRWLI
HRWLI
HRWLI
RWHPI
SDATWH
HDATWH
SDDATO
DATTR
DACKAD
ACKTR
t
= 4 + DT/8.
This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), o perating at t
use the preceding timing specification of the same name.
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
t
setup times greater than 19 + 3DT/4, then ACK is valid 15.5 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
DACKAD
SRWLI
(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
READ ACCESS
WRITE ACCESS
ADDRESS
CLKIN
DATA
(OUT)
DATA
ACK
WR
(IN)
RD
SW
Address, SW Setup before CLKIN
Address, SW Hold before CLKIN
RD/WR Low Setup before CLKIN
RD/WR Low Hold after CLKIN
RD/WR Low Hold after CLKIN
44 MHz/50 MHz
RD/WR Pulse High
Data Setup before WR High
Data Hold after WR High
Data Delay after CLKIN
Data Disable after CLKIN
ACK Delay after Address, SW
ACK Disable after CLKIN
2
3
4
4
t
SDDATO
1
Min
14 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
–3.5 – 5DT/16
3
3
1
0 – DT/8
–1 – DT/8
t
DACKAD
ADSP-21061 (5 V)
t
SADRI
memory space). The bus master must meet these (bus slave)
timing requirements.
Max
5 + DT/2
8 + 7DT/16
8 + 7DT/16
19 + 5DT/16
7 – DT/8
8
6 – DT/8
ACKTR
t
t
SRWLI
SRWLI
.
t
HADRI
t
SDATWH
ADSP-21061/ADSP-21061L
Min
14 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
–3.5 – 5DT/16
3
3
1
0 – DT/8
–1 – DT/8
t
t
t
HDATWH
ADSP-21061L (3.3 V)
HRWLI
HRWLI
t
t
DATTR
ACKTR
CK
<25 ns. For all other devices,
t
t
Max
5 + DT/2
8 + 7DT/16
8 + 7DT/16
19 + 5DT/16
7 – DT/8
8
6 – DT/8
RWHPI
RWHPI
SRWLI
(min)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns