ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 34

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Serial Ports
Parameter
External Clock
Timing Requirements:
t
t
t
t
t
t
Internal Clock
Timing Requirements:
t
t
t
t
External or Internal Clock
Switching Characteristics:
t
t
External Clock
Switching Characteristics:
t
t
t
t
Internal Clock
Switching Characteristics:
t
t
t
t
t
Enable and Three-State
Switching Characteristics:
t
t
t
t
t
t
External Late Frame Sync
Switching Characteristics:
t
t
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOTES
1
2
3
4
ADSP-21061/ADSP-21061L
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HODTE
DFSI
HOFSI
DDTI
HDTI
SCLKIW
DDTEN
DDTTE
DDTIN
DDTTI
DCLK
DPTR
DDTLFSE
DDTENFS
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external. TFS is 0 ns minimum from drive edge.
Referenced to drive edge.
MCE = 1, TFS enable and TFS valid follow t
TFS/RFS Setup before TCLK/RCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup before TCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
RFS Delay after RCLK (Internally Generated RFS)
RFS Hold after RCLK (Internally Generated RFS)
TFS Delay after TCLK (Internally Generated TFS)
TFS Hold after TCLK (Internally Generated TFS)
Transmit Data Delay after TCLK
Transmit Data Hold after TCLK
TFS Delay after TCLK (Internally Generated TFS)
TFS Hold after TCLK (Internally Generated TFS)
Transmit Data Delay after TCLK
Transmit Data Hold after TCLK
TCLK/RCLK Width
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Delay from CLKIN
SPORT Disable after CLKIN
Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 0
Data Enable from late FS or MCE = 1, MFD = 0
1
; RFS Setup before RCLK
1
1
DDTLFSE
3
3
1
1
3
3
3
3
3
3
1, 2
1, 2
1
4
and t
DDTENFS
4
3
3
3
3
3
3
.
1
Min
3.5
4
1.5
4
9
t
8
1
3
3
3
3
5
–1.5
0
(t
4.5
0
3.5
CK
SCLK
ADSP-21061 (5 V)
/2) – 2.5
Max
13
13
16
4.5
7.5
(t
10.5
3
22 + 3DT/8
17
12
SCLK
/2) + 2.5
Min
3.5
4
1.5
4
9
t
8
1
3
3
3
3
5
–1.5
0
(t
3.5
–0.5
3.5
CK
SCLK
ADSP-21061L (3.3 V)
/2) – 2.5
Max
13
13
16
4.5
7.5
(t
10.5
3
22 + 3DT/8
17
12
SCLK
/2) + 2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns