MT55L128L18P1 Micron Semiconductor Products, Inc., MT55L128L18P1 Datasheet

MT55L128L18P1

Manufacturer Part Number

MT55L128L18P1

Description

2Mb ZBT SRAM, 3.3V Vdd, 3.3V I/O, Pipelined,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT55L128L18P1.pdf (18 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

MT55L128L18P1F-10

Manufacturer:

MICRON/美光

Quantity:

20 000

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NOT RECOMENDED FOR NEW DESIGNS

2Mb

ZBT

FEATURES

• High frequency and 100 percent bus utilization

• Fast cycle times: 7.5ns and 10ns

• Single +3.3V ±5% power supply

• Advanced control logic for minimum control signal

• Individual BYTE WRITE controls may be tied LOW

• Single R/W# (read/write) control pin

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

• Internally self-timed, fully coherent WRITE

• Internally self-timed, registered outputs eliminate

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature (optional)

• Pin/function compatibility with 4Mb, 8Mb, and

• 100-pin TQFP package

• Automatic power-down

OPTIONS

• Timing (Access/Cycle/MHz)

• Configurations

• Package

• Temperature

2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM

MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02

interface

I/Os and control signals

the need to control OE#

16Mb ZBT SRAM

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

128K x 18

100-pin TQFP

Commercial (0°C to +70°C)

64K x 32

64K x 36

SRAM

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

MT55L128L18P1T-10

Part Number Example:

MT55L128L18P1

MT55L64L32P1

MT55L64L36P1

MARKING

None

-7.5

-10

MT55L128L18P1, MT55L64L32P1,

MT55L64L36P1

3.3V V

GENERAL DESCRIPTION

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM

core with advanced synchronous peripheral circuitry

and a 2-bit burst counter. These SRAMs are optimized

for 100 percent bus utilization, eliminating turnaround

cycles for READ to WRITE, or WRITE to READ, transi-

tions. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock in-

put (CLK). The synchronous inputs include all ad-

dresses, all data inputs, chip enable (CE#), two addi-

tional chip enables for easy depth expansion (CE2,

CE2#), cycle start input (ADV/LD#), synchronous clock

enable (CKE#), byte write enables (BWa#, BWb#, BWc#

and BWd#) and read/write (R/W#).

(OE#, which may be tied LOW for control signal minimi-

zation), clock (CLK) and snooze enable (ZZ, which may

be tied LOW if unused). There is also a burst mode pin

(MODE) that selects between interleaved and linear

burst modes. MODE may be tied HIGH, LOW or left

unconnected if burst is unused. The data-out (Q), en-

abled by OE#, is registered by the rising edge of CLK.

WRITE cycles can be from one to four bytes wide as

controlled by the write control inputs.

*JEDEC-standard MS-026 BHA (LQFP).

The Micron

The MT55L128L18P1 and MT55L64L32/36P1

Asynchronous inputs include the output enable

3.3V I/O, PIPELINED ZBT SRAM

2Mb: 128K x 18, 64K x 32/36

, 3.3V I/O

Zero Bus Turnaround

100-Pin TQFP*

™

(ZBT

) SRAM

Related parts for MT55L128L18P1

MT55L128L18P1 Summary of contents

Page 1

... Temperature Commercial (0°C to +70°C) Part Number Example: MT55L128L18P1T-10 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM MT55L128L18P1, MT55L64L32P1, MT55L64L36P1 3 ...

Page 2

... CE2 CE2# NOTE: Functional Block Diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...

Page 3

... DQd 50 * Pins 50, 83, and 84 are reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa# con- trols DQa pins ...

Page 4

... SA 100 * NC for x32 version, DQPx for x36 version. ** Pins 50, 83, and 84 are reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP x18 ...

Page 5

... I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM SYMBOL TYPE SA0 Input Synchronous Address Inputs: These inputs are SA1 registered and must meet the setup and hold times S A around the rising edge of CLK ...

Page 6

... I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM SYMBOL TYPE R/W# Input Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs ...

Page 7

... WRITE Byte “c” WRITE Byte “d” WRITE All Bytes WRITE ABORT/NOP NOTE: Using R/W# and byte write(s), any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM THIRD ADDRESS (INTERNAL) X...X01 X...X00 X...X11 X ...

Page 8

... NOTE STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM State Diagram for ZBT SRAM DS ...

Page 9

... The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle. 11. The address counter is incremented for all CONTINUE BURST cycles. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM ADDRESS CE# CE2# CE2 ZZ ADV/ R/W# BWx OE# CKE# CLK ...

Page 10

... Q should never exceed This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...

Page 11

... Typical values are measured at 3.3V, 25°C, and 10ns cycle time. 4. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM CONDITIONS or V ...

Page 12

... A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM , +3.3V ± ...

Page 13

... SRAM timing is dependent upon the capacitive load- ing on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM Output Load Equivalents to 3.0V SS ...

Page 14

... I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM the ZZ pin becomes a logic HIGH, I after the time tion pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pend- ing operations are completed ...

Page 15

... Data coherency is provided for all possible operations READ is initiated, the most current data is used. The most recent data may be from the input data register. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM READ/WRITE TIMING ...

Page 16

Page 17

... ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 3.3V I/O, PIPELINED ZBT SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) 0.625 14.00 ± ...

Page 18

... Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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