MT55L128L18P1 Micron Semiconductor Products, Inc., MT55L128L18P1 Datasheet - Page 16

• Manufacturer Part Number: MT55L128L18P1
• Description: 2Mb ZBT SRAM, 3.3V Vdd, 3.3V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
NOP, STALL AND DESELECT TIMING PARAMETERS
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
COMMAND
SYMBOL
t
t
KHQX
KHQZ
ADDRESS
ADV/LD#
BWx#
R/W#
CKE#
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
CLK
CE#
DQ
performed during this cycle.
recent data may be from the input data register.
WRITE
D(A1)
A1
1
MIN
1.5
1.5
-7.5
Q(A2)
READ
A2
2
MAX
3.5
NOP, STALL, AND DESELECT CYCLES
MIN
1.5
1.5
STALL
3
-10
MAX
3.5
D(A1)
Q(A3)
READ
A3
4
UNITS
ns
ns
Q(A2)
16
WRITE
D(A4)
A4
5
3.3V I/O, PIPELINED ZBT SRAM
STALL
2Mb: 128K x 18, 64K x 32/36
6
Q(A3)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
7
DON’T CARE
D(A4)
Q(A5)
READ
A5
8
DESELECT
9
©2002, Micron Technology, Inc.
t
KHQX
UNDEFINED
CONTINUE
DESELECT
Q(A5)
10
t
KHQZ