MT55L128L18P1 Micron Semiconductor Products, Inc., MT55L128L18P1 Datasheet - Page 6

• Manufacturer Part Number: MT55L128L18P1
• Description: 2Mb ZBT SRAM, 3.3V Vdd, 3.3V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
PIN DESCRIPTIONS (continued)
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
40, 55, 60, 67, 71,
(a)
5, 10, 17, 21, 26,
(b)
14–16, 41, 65,
28–30, 51-53,
56, 57, 75, 78,
38, 39, 42, 43
68, 69, 72, 73
18, 19, 22, 23
54, 61, 70, 77
4, 11, 20, 27,
1-3, 6, 7, 25,
TQFP (x18)
58, 59, 62, 63,
79, 95, 96
8, 9, 12, 13,
83, 84
66, 91
76, 90
88
74
24
31
50
TQFP (x32/x36)
14–16, 41, 65,
26, 40, 55, 60,
38, 39, 42, 43
56–59, 62, 63
72–75, 78, 79
22–25, 28, 29
54, 61, 70, 77
67, 71, 76, 90
4, 11, 20, 27,
5, 10, 17, 21,
(c)
(b)
(d)
(a)
2, 3, 6–9,
12, 13
83, 84
66, 91
N/A
52, 53,
68, 69,
18, 19,
88
51
80
30
31
50
1
NC/DQPa
NC/DQPb
NC/DQPd
NC/DQPc
SYMBOL
(LBO#)
MODE
NC/SA
R/W#
V
DQb
DQd
DNU
DQa
DQc
V
N C
V
N F
DD
DD
SS
Q
Output pins; Byte “c” is DQc pins; Byte “d” is DQd pins. Input
Supply Power Supply: See DC Electrical Characteristics and
Supply Isolated Output Buffer Supply: See DC Electrical
Supply Ground: GND.
Input/
Input
Input
TYPE
NC/
I/O
N C
N C
–
–
6
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a
new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs
occur if all byte write enables are LOW.
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
SRAM Data I/Os: Byte “a” is DQa pins; Byte “b” is DQb
data must meet setup and hold times around the rising
edge of CLK.
No Connect/Data Bits: On the x32 version, these pins are
no connect (NC) and can be left floating or connected
to GND to minimize thermal impedance. On the x36
version, these bits are DQs.
No Connect: These pins can be left floating or
connected to GND to minimize thermal impedance.
Mode: This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
No Connect: NC pin 50 is reserved as an address bit
for the higher-density 4Mb ZBT SRAM. This pin can be
left floating or connected to GND to minimize thermal
impedance.
No Function: These pins are internally connected to the
die and will have the capacitance of an input pin. It is
allowable to leave these pins unconnected or driven by
signals. Pins 83 and 84 are reserved as address bits for the
8Mb and 16Mb ZBT SRAMs.
Operating Conditions for range.
Characteristics and Operating Conditions for range.
3.3V I/O, PIPELINED ZBT SRAM
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.