MT55L128L18P1 Micron Semiconductor Products, Inc., MT55L128L18P1 Datasheet - Page 3

• Manufacturer Part Number: MT55L128L18P1
• Description: 2Mb ZBT SRAM, 3.3V Vdd, 3.3V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
GENERAL DESCRIPTION (continued)
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
simplify WRITE cycles. This allows self-timed WRITE
PIN ASSIGNMENT TABLE
* Pins 50, 83, and 84 are reserved for address expansion.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
All READ, WRITE, and DESELECT cycles are initi-
To allow for continuous, 100 percent use of the data
Address and write control are registered on-chip to
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
x18
NC
NC
NC
NC
NC
NC
V
V
V
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
V
V
V
V
x32
V
V
V
NC
DD
DD
DD
DD
DD
DD
SS
S S
SS
SS
Q
Q
Q
DQPc
DQPc
DQd
DQd
DQd
DQd
DQd
DQd
DQc
DQc
DQc
DQc
DQc
DQc
DQc
x36
PIN # x18
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
MODE (LBO#)
NC/SA*
V
DNU
DNU
DNU
DNU
DQd
DQd
x32
SA1
SA0
V
V
V
NC
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
DD
DD
S S
SS
Q
DQPd
DQd
DQd
x36
3
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only avail-
able on the x18 and x36 versions.
power supply, and all inputs and outputs are LVTTL-
compatible. The device is ideally suited for systems
requiring high bandwidth and zero bus turnaround
delays.
sramds) for the latest data sheet.
PIN # x18
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Micron’s 2Mb ZBT SRAMs operate from a +3.3V V
Please refer to Micron’s Web site
3.3V I/O, PIPELINED ZBT SRAM
DQPa
DQa
DQa
DQa
DQa
2Mb: 128K x 18, 64K x 32/36
NC
NC
NC
NC
NC
NC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
V
V
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
x32
V
V
V
V
V
V
NC
DD
DD
ZZ
DD
DD
DD
SS
SS
SS
SS
Q
Q
Q
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
x36
PIN # x18
100
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
(www.micron.com/
NC
NC
NC
NC
SA
©2002, Micron Technology, Inc.
ADV/LD#
OE# (G#)
BWa#
BWb#
BWd# BWd#
BWc# BWc#
V
R/W#
CKE#
CE2#
DQb
DQb
NF*
NF*
CLK
CE2
CE#
x32
V
V
V
NC
SA
SA
SA
SA
DD
DD
S S
SS
Q
DQPb
DQb
DQb
x36
DD