MT55L128L18P1 Micron Semiconductor Products, Inc., MT55L128L18P1 Datasheet - Page 12

• Manufacturer Part Number: MT55L128L18P1
• Description: 2Mb ZBT SRAM, 3.3V Vdd, 3.3V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0°C ≤ T
NOTE: 1. Measured as HIGH above V
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
2. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
3. This parameter is sampled.
4. Output loading is specified with C
5. Transition is measured ±200mV from steady state voltage.
6. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
8. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
turnaround timing.
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
A
≤ +70°C; V
IH
DD
and LOW below V
, V
L
DD
= 5pF as shown in Figure 2.
Q = +3.3V ±0.165V)
IL
.
12
SYMBOL
t
t
t
t
KHQX1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KHQV
KHQX
KHKH
KHQZ
GHQZ
AVKH
DVKH
KHAX
KHDX
KHKL
KLKH
GLQV
GLQX
EVKH
CVKH
KHEX
KHCX
f
KF
3.3V I/O, PIPELINED ZBT SRAM
2Mb: 128K x 18, 64K x 32/36
MIN
7.5
2.2
2.2
1.5
1.5
1.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
-7.5
MAX
133
4.2
3.5
4.2
4.2
MIN
3.5
3.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
10
0
-10
MAX
100
5.0
3.5
5.0
5.0
UNITS
©2002, Micron Technology, Inc.
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
NOTES
1
1
2
6
7
7
7
7
7
7
7
7