ACS8525T Semtech, ACS8525T Datasheet - Page 12

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

sources are active and valid, the source with the highest
programmed priority is selected, but if this source fails,
the next-highest source is selected, and so on.
Restoration of repaired SECs is handled carefully to avoid
inadvertent disturbance of the output clock. For this, the
ACS8525 has two modes of operation; Revertive and
Non-revertive.
In Revertive mode, if a re-validated (or newly validated)
source has a higher priority than the SEC which is
currently selected, a switchover will take place. Many
applications prefer to minimize the clock switching events
and choose Non-revertive mode.
In Non-revertive mode, when a re-validated (or newly
validated) source has a higher priority, then the selected
source will be maintained. The re-validation of the SEC will
be flagged in the sts_sources_valid register (Reg. 0E and
0F) and, if not masked, will generate an interrupt.
Selection of the re-validated source can take place under
software control or if the currently selected source fails.
To enable software control, the software should briefly
enable Revertive mode to effect a switch-over to the
higher priority source. When there is a reference available
with higher priority than the selected reference, there will
be NO change of SEC as long as the Non-revertive mode
remains on, and the currently selected source is valid. A
failure of the selected reference will always trigger a
switch-over regardless of whether Revertive or
Non-revertive mode has been chosen.
Forced Control Selection
A configuration register, force_select_reference_source
Reg. 33, controls both the choice of automatic or forced
selection and the selection itself (when forced selection is
required). For Automatic choice of source selection, the 4
LSB bit value force_select_SEC_input is set to all zeros or
all ones (default). To force a particular input, the bit value
is set according to the description for Reg. 33. Forced
selection is not the normal mode of operation, and
force_select_SEC_input defaults to the all-ones value on
reset, thereby adopting the automatic selection of the
SEC.
Automatic Control Selection - Priority Table
When an automatic selection is required, the
force_select_reference_source register LSB 4 bits
(force_select_SEC_input) must be set to all zeros or all
ones.
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 12
The Priority Table register cnfg_ref_selection_priority,
occupying three 8-bit register addresses (Reg. 19, 1A and
1C), is organized as one 4-bit word per input SEC port.
Each 4 bit word represents the desired priority of that
particular port. Unused ports should be given the value
0000 in the relevant register to indicate they are not to be
included in the priority table. On power-up, or following a
reset, the input priority configuration is set to the default
values defined by Table 4. The selection priority values
are all relative to each other, with lower-valued numbers
taking higher priorities. Each SEC should be given a
unique number; the valid values are 1 to 15 (dec). A value
of 0 disables the SEC. However if two or more inputs are
given the same priority number those inputs will be
selected on a first in, first out basis. If the first of two same
priority number sources goes invalid the second will be
switched in. If the first then becomes valid again, it
becomes the second source on the first in, first out basis,
and there will not be a switch. If a third source with the
same priority number as the other two becomes valid, it
joins the priority list on the same first in, first out basis.
There is no implied priority based on the channel
numbers. Revertive/Non-revertive mode has no effect on
sources with the same priority value.
The priority of Sync inputs is determined by the priority of
their associated SEC inputs. The Sync inputs do not have
their own separate priority table.
Ultra Fast Switching
An SEC is normally disqualified after the Leaky Bucket
monitor thresholds have been crossed. An option for a
faster disqualification has been implemented, whereby if
Reg. 48 Bit 5 (ultra_fast_switch) is set, then a loss of
activity of just two or three reference clock cycles causes
a reference switch, and sets the DPLL1_main_ref_failed
bit (see Reg. 06 Bit 6) which raises an interrupt (if not
masked).
The sts_interrupts register Reg. 06 Bit 6
(DPLL1_main_ref_failed) is used to flag inactivity on the
reference that the device is locked to much faster than
the activity monitors can support. If Reg. 48 Bit 6 of the
cnfg_monitors register (los_flag_on_TDO) is set, then the
state of this bit is driven onto the TDO pin of the device.
Note...The flagging of the loss of the main reference failure on
TDO is simply allowing the status of the sts_interrupts bit
DPLL1_main_ref_failed to be reflected in the state of the TDO
output pin. The pin will, therefore, remain High until the
interrupt is cleared. This functionality is not enabled by default
so the usual JTAG functions can be used. When the TDO output
from the ACS8525 is connected to the TDI pin of the next
ACS8525 LC/P
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