ACS8525T Semtech, ACS8525T Datasheet - Page 40

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Table 15 Register Map (cont...)
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
RO = Read Only
R/W = Read/Write
cnfg_interrupt_mask (R/W) [7:0] 43 00 Set to 0
cnfg_freq_divn (R/W)
cnfg_monitors (R/W)
cnfg_registers_source_select
(R/W)
cnfg_freq_lim_ph_loss
cnfg_upper_threshold_0 (R/W)
cnfg_lower_threshold_0 (R/W)
cnfg_bucket_size_0 (R/W)
cnfg_decay_rate_0 (R/W)
cnfg_upper_threshold_1 (R/W)
cnfg_lower_threshold_1 (R/W)
cnfg_bucket_size_1 (R/W)
cnfg_decay_rate_1 (R/W)
cnfg_upper_threshold_2 (R/W)
cnfg_lower_threshold_2 (R/W)
cnfg_bucket_size_2 (R/W)
cnfg_decay_rate_2 (R/W)
cnfg_upper_threshold_3 (R/W)
cnfg_lower_threshold_3 (R/W)
cnfg_bucket_size_3 (R/W)
cnfg_decay_rate_3 (R/W)
cnfg_output_frequency (R/W)
cnfg_DPLL2_frequency (R/W)
cnfg_DPLL1_frequency (R/W)
cnfg_DPLL2_bw (R/W)
cnfg_DPLL1_locked_bw (R/W)
cnfg_DPLL1_acq_bw (R/W)
cnfg_DPLL2_damping (R/W)
cnfg_DPLL1_damping (R/W)
cnfg_DPLL2_PD2_gain (R/W)
cnfg_DPLL1_PD2_gain (R/W)
cnfg_phase_offset (R/W)
cnfg_PBO_phase_offset (R/W)
cnfg_phase_loss_fine_limit (R/W) 73 A2
cnfg_DPLL_freq_limit (R/W) [9:8] 42 00
Register Name
(MFrSync/FrSync) 63 C0 MFrSync_en
(Output O2) 61 06
(Output O1) 62 80
[23:16] 45 00 Sync_ip_alarm
[15:8] 44 00 operating_
[13:8] 47 3F
[15:8] 71 00
[7:0]. 46 FF
[7:0] 70 00
53 01
57 01
5B 01
5F
67 10
72 00
48 04
4B 00
4D
50 06
51 04
52 08
54 06
55 04
56 08
58 06
59 04
5A
5C 06
5D 04
5E
64 00
65 01 DPLL2_meas_
66 00
69 11
6A
6B 13
6C C2 DPLL2_PD2_
6D C2 DPLL1_PD2_
08
08
01
13
mode
freq_lim_ph_
loss
DPLL1_ph
gain_enable
gain_enable
fine_limit_en
7 (MSB)
Set to 0
main_ref_
failed
los_flag_on_
TDO
FrSync_en
APLL2_for_
DPLL1_E1/
DS1
noact_ph_loss
6
output_freq_O1
lower_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - reset threshold)
lower_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - reset threshold)
lower_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - reset threshold)
lower_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - reset threshold)
upper_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - set threshold)
upper_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - set threshold)
upper_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - set threshold)
upper_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - set threshold)
DPLL2_PD2_gain_alog_8k
DPLL1_PD2_gain_alog_8k
DPLL2_PD2_gain_alog
DPLL1_PD2_gain_alog
Bucket_size_0_value (Activity alarm, Config. 0, Leaky Bucket - size)
Bucket_size_1_value (Activity alarm, Config. 1, Leaky Bucket - size)
Bucket_size_2_value (Activity alarm, Config. 2, Leaky Bucket - size)
Bucket_size_3_value (Activity alarm, Config. 3, Leaky Bucket - size)
SEC2 DIFF
ultra_fast_
switch
narrow_en
FINAL
Page 40
DPLL1_freq_to_APLL2
5
divn_value [7:0] (divide Input frequency by n)
SEC1 DIFF
ext_switch
DPLL1_DPLL2
_select
phase_offset_value[15:8]
phase_offset_value [7:0]
4
divn_value [13:8] (divide Input frequency by n)
Data Bit
SEC2 TTL
PBO_freeze
3
PBO_phase_offset
SEC1 TTL
Set to 0
PBO_en
ACS8525 LC/P
2
output_freq_O2
DPLL2_PD2_gain_digital
DPLL1_PD2_gain_digital
phase_loss_fine_limit
DPLL2_frequency
DPLL1_frequency
DPLL2_damping
DPLL1_damping
Bits[9:8] of
cnfg_DPLL_freq_limit
alarm, Config. 0, Leaky Bucket -
alarm, Config. 1, Leaky Bucket -
alarm, Config. 2, Leaky Bucket -
alarm, Config. 3, Leaky Bucket -
DPLL1_acquisition_bandwidth
decay_rate_0_value (Activity
decay_rate_1_value (Activity
decay_rate_2_value (Activity
decay_rate_3_value (Activity
DPLL1_locked_bandwidth
1
DPLL2_bandwidth
DATASHEET
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leak rate)
leak rate)
leak rate)
leak rate)
SEC3
0 (LSB)