ACS8525T Semtech, ACS8525T Datasheet - Page 85

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
DPLL2_PD2_
gain_enable
Register Name
DPLL1_PD2_
gain_enable
Bit No.
Bit No.
Bit 7
[2:0]
Bit 7
[6:4]
7
3
6C (cont...)
6D
cnfg_DPLL2_PD2_gain
Description
DPLL2_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. This setting is always used if automatic gain
selection is disabled in Bit 7,
DPLL2_PD2_gain_enable.
cnfg_DPLL1_PD2_gain
Description
DPLL1_PD2_gain_enable
DPLL1_PD2_gain_alog
Register to control the gain of Phase Detector 2
when locking to a reference, higher than 8 kHz, in
analog feedback mode. This setting is not used if
automatic gain selection is disabled in Bit 7,
DPLL1_PD2_gain_enable.
Not used.
Bit 6
Bit 6
DPLL2_PD2_gain_alog
DPLL1_PD2_gain_alog
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 85
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL2.
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL1.
Bit Value
Bit Value
Bit 3
Bit 3
0
1
-
-
-
Value Description
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Value Description
DPLL2 Phase Detector 2 not used.
DPLL2 Phase Detector 2 gain enabled and choice of
gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
- analog feedback at 8 kHz
Gain value of Phase Detector 2 when locking to a
high frequency reference in analog feedback mode.
-
Bit 2
Bit 2
DPLL2_PD2_gain_digital
DPLL1_PD2_gain_digital
Default Value
Default Value
ACS8525 LC/P
Bit 1
Bit 1
DATASHEET
www.semtech.com
1100 0010
1100 0010
Bit 0
Bit 0