ACS8525T Semtech, ACS8525T Datasheet - Page 93

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
2k_8k_from_
DPLL2
Bit No.
Bit No.
Bit 7
[5:0]
Bit 7
[6:4]
7
3
2
79 (cont...)
7A
cnfg_phase_alarm_timeout
Description
timeout_value
Phase alarms can only be raised on an input when
DPLL1 is attempting to lock to it. Once an input has
been rejected due to a phase alarm, there is no way
to measure whether it is good again, because it is
no longer selected by the DPLL. The phase alarms
can either remain until reset by software, or timeout
after 128 seconds, as selected in Reg. 34 Bit 6,
phalarm_timeout.
cnfg_sync_pulses
Description
2k_8k_from_DPLL2
Register to select the source (DPLL1 or DPLL2) for
the 2 kHz and 8 kHz outputs available from O1 and
O2.
Not used.
8k_invert
Register bit to invert the 8 kHz output from FrSync.
8k_pulse
Register bit to enable the 8 kHz output from FrSync
to be either pulsed or 50:50 duty cycle. Output 02
must be enabled to use “pulsed output” mode on
the FrSync output, and then the pulse width on the
FrSync output will be equal to the period of the
output programmed on O2.
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 93
timeout_value (in two-second intervals)
(R/W) Register to configure how
long before a phase alarm is
raised on an input.
(R/W) Register to configure the
Sync outputs available from
FrSync and MFrSync and select
the source for the 2 kHz and
8 kHz outputs from O1 and O2.
8k_invert
Bit Value
Bit Value
Bit 3
Bit 3
0
1
0
1
0
1
-
-
Value Description
This 6-bit unsigned integer represents the length of
time before a phase alarm will be raised on an
input. The value multiplied by 2 gives the time in
seconds. This time value is the time that the
controlling state machine will spend in Pre-locked,
Pre-locked2 or Phase-lost modes before setting the
phase alarm on the selected input.
8k_pulse
Value Description
2/8 kHz on O1 and O2 generated from DPLL1.
2/8 kHz on O1 and O2 generated from DPLL2.
-
8 kHz FrSync output not inverted.
8 kHz FrSync output inverted.
8 kHz FrSync output not pulsed.
8 kHz FrSync output pulsed.
Bit 2
Bit 2
Default Value
Default Value
2k_invert
ACS8525 LC/P
Bit 1
Bit 1
DATASHEET
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0011 0010
0000 0000
2k_pulse
Bit 0
Bit 0