ACS8525T Semtech, ACS8525T Datasheet - Page 80

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Address (hex):
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
DPLL2_meas_
DPLL1_ph
Bit No.
Bit 7
[5:4]
[2:0]
3
65 (cont...)
cnfg_DPLL1_frequency
APLL2_for_
DPLL1_E1/DS1
Description
DPLL1_freq_to_APLL2
Register to select the frequency/mode of DPLL1
which is driven to the APLL2 when selected by Bit 6,
APLL2_for_DPLL1_E1/DS1.
Register to select DPLL1’s frequency driven to the
APLL2 (DPLL1 mode*) when selected by Bit 6,
APLL2_for_DPLL1_E1/DS1 ; and consequently the
APLL output frequency in the T4 path.
*Note that this is not the operating frequency of
DPLL1 itself - which is fixed at outputting
77.76 MHz - but is the multiplied output from the LF
Output DFS block. See Figure 5 “PLL Block
Diagram” on page 15.
Not used.
DPLL1_frequency
Register to configure the frequency driven to APLL1
(DPLL1 mode*) and consequently the APLL output
frequency in the T0 path. This register affects the
frequencies available at outputs O1 and O2, see
Reg. 61 - Reg. 63.
*Note that this is not the operating frequency of the
DPLL1 itself - which is fixed at outputting
77.76 MHz - but is the multiplied output from the LF
Output DFS block. See Figure 5 “PLL Block
Diagram” on page 15.
Note...001 is the only selection that does not
bypass APLL3. All other selections use digital
feedback.
Bit 6
Bit 5
DPLL1_freq_to_APLL2
Description
Bit 4
FINAL
Page 80
(R/W) Register to configure
DPLL1 and several other
parameters.
Bit Value
Bit 3
000
001
010
011
100
101
110
111
00
01
10
11
-
Value Description
DPLL1 mode = 12E1, giving APLL2 output
frequency (before dividers) = 98.304 MHz.
DPLL1 mode = 16E1, giving APLL2 output
frequency (before dividers) = 131.072 MHz.
DPLL1 mode = 24DS1, giving APLL2 output
frequency (before dividers) = 148.224 MHz.
DPLL1 mode = 16DS1, giving APLL2 output
frequency (before dividers) = 98.816 MHz.
-
DPLL1 mode = 77.76 MHz, digital feedback, APLL1
output frequency (before dividers) = 311.04 MHz.
DPLL1 mode = 77.76 MHz, analog feedback, APLL1
output frequency (before dividers) = 311.04 MHz.
DPLL1 mode = 12E1, giving APLL1 output
frequency (before dividers) = 98.304 MHz.
DPLL1 mode = 16E1, giving APLL1 output
frequency (before dividers) = 131.072 MHz.
DPLL1 mode = 24DS1, giving APLL1 output
frequency (before dividers) = 148.224 MHz.
DPLL1 mode = 16DS1, giving APLL1 output
frequency (before dividers) = 98.816 MHz.
Not used.
Not used.
Bit 2
DPLL1_frequency
Default Value
ACS8525 LC/P
Bit 1
DATASHEET
www.semtech.com
0000 0001
Bit 0