ACS8525T Semtech, ACS8525T Datasheet - Page 21

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Output Phase Adjustment
Phase Detector Controls
Advanced Phase Detector Controls
The phase detector actually comprises two different
phase detector types, PD1 and PD2. Their interworking
and selection algorithms are beyond the scope of this
datasheet, however it should be noted the gain of only
PD2 is adjustable by configuration, in the following
feature:
Phase Monitors
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Programmable Input to Output phase offset
adjustment, ±200 ns, 6 ps resolution step size
(Reg. 70 and 71)
Programmable mean offset on Phase Build-out event
(PBO phase offset on source switching) - disturbance
down to ±5 ns. (Reg. 72 Bits [5:0]). Requires PBO to
be on (Reg. 48 Bit 3)
Multi-cycle phase detection - Course phase lock &
capture range on/off (Reg. 74 Bit 6) and selectable
range from ±1 to 8191 UI in 13 steps (Reg. 74 Bits
[3:0]). If selected, this feature increases jitter and
wander tolerance to a maximum of 8192 UI (normally
limited to ±0.5 UI)
Use of coarse phase detector result in DPLL algorithm,
on/off (Reg. 74 Bit 6) - speeds up phase locking
Limit DPLL1 Integral when at DPLL frequency limit,
on/off (Reg. 3B Bit 3) - reduces overshoot
Anti-noise filter for low frequency inputs, on/off
(Reg. 76 Bit 7)
DPLL1 PD2 gain control enable, on/off (Reg. 6D
Bit 7)
If on, this allows automatic gain selection according to
the type of feedback to the DPLL (For the digital
feedback setting, the gain used for PD2 is given by
Reg. 6D Bits [2:0]). If off, PD2 is not used.
Adjustable gain settings for PD2 (with auto switching
enabled), for the following feedback cases:
Input phase measured at DPLL1 or DPLL2. DPLL
select (Reg. 4B Bit 4), 16-bit phase status
(Reg. 77/Reg. 78)
Phase measured between two inputs (uses DPLL2’s
PFD (Reg. 65 Bit 7))
• Digital feedback (Reg. 6D Bits [2:0])
• Analog feedback (all frequencies above 8 kHz)
• Analog 8k (or less) feedback (Reg. 6B Bits [2:0])
(Reg. 6D Bits [6:4])
FINAL
Page 21
DPLL2 Main Features
The main features of DPLL2 are:
DPLL2 Advanced Features
The advanced features are the same as those for DPLL1,
with DPLL2 using the configuration values for DPLL1, with
the following exceptions:
Advanced Phase Detector Controls
Always locked to DPLL1
A single programmable bandwidth control: 18, 35 or
70 Hz
Damping factor, (For optional faster locking and
peaking control) Factors = 1.2, 2.5, 5, 10 or 20.
Digital feedback, on/off (Reg. 35 Bit 6)
Output frequency selection (Reg. 64)
Can provide the source for the 2 kHz and 8 kHz
outputs available at Outputs 01 and 02 (Reg. 7A Bit 7)
Can use the phase detector in DPLL2 to measure the
input phase difference between two inputs
Selectable DPLL2 digital feedback, on/off (Reg. 64
Bit 6)
PD2 gain control enable, on/off (Reg. 6C, Bit 7)
If on, this allows automatic gain selection according to
the type of feedback to the DPLL (For the digital
feedback setting, the gain used for PD2 is given by
(Reg. 6C Bits [2:0]). If off, PD2 is not used.
Adjustable gain settings for PD2 (with auto switching
enabled), for the following feedback cases:
• DS3/E3 support (44.736 MHz / 34.368 MHz)
• Low jitter E1/DS1 options independent of rates
• Frequencies of n x E1/DS1 including 16 and 12 x
• Squelched (clock off)
• Digital feedback (Reg. 6C Bits [2:0])
• Analog feedback (all frequencies above 8K)
• Analog 8k (or less) feedback (Reg. 6A Bits [2:0])
independent of rates from DPLL1
from DPLL1
E1, and 16 and 24 x DS1 supported
(Reg. 6C Bits [6:4])
ACS8525 LC/P
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