ACS8525T Semtech, ACS8525T Datasheet - Page 14

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

via register control, which provides a range of output
frequencies and levels of jitter performance.
The DPLLs give a stable and consistent level of
performance that can be easily programmed for different
dynamic behavior or operating range. They are not
affected by operating conditions or silicon process
variations. Digital Synthesis is used to generate all
required SONET/SDH output frequencies. The digital logic
operates at 204.8 MHz that is multiplied up from the
external 12.800 MHz oscillator module. Hence the best
resolution of the output signals from the DPLLs is one
204.8 MHz cycle or 4.9 ns.
Additional resolution and lower final output jitter is
provided by a de-jittering APLL that reduces the 4.9 ns p-p
jitter from the digital down to 500 ps p-p and 60 ps RMS
as typical final outputs measured broadband (from 10 Hz
to 1 GHz).
This arrangement combines the advantages of the
flexibility and repeatability of a DPLL with the low jitter of
an APLL. The DPLLs in the ACS8525 are programmable
for PLL parameters of bandwidth (18, 35 and 70 Hz),
damping factor (from 1.2 to 20), frequency acceptance
and output range (from 0 to 80 ppm, typically 9.2 ppm),
input frequency (12 common SONET/SDH spot
frequencies) and input-to-output phase offset (in 6 ps
steps up to 200 ns). There is no requirement to
understand the loop filter equations or detailed gain
parameters since all high level factors such as overall
bandwidth can be set directly via registers in the
microprocessor interface. No external critical
components are required for either the internal DPLLs or
APLLs, providing another key advantage over traditional
discrete designs.
Either the software or an internal state machine controls
the operation of DPLL1. The state machine for DPLL2 is
very simple and cannot be manually/externally controlled.
One additional feature of DPLL2 is the ability to measure
a phase difference between two inputs.
DPLL1 always produces an output at 77.76 MHz to feed
the APLL, regardless of the frequency selected at the
output pins or the locking frequency (frequency at the
input of the Phase and Frequency Detector- PFD).
DPLL2 can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies,
which cannot be easily related to 77.76 MHz. If DPLL2 is
enabled, it locks to the 8 kHz from DPLL1. This is because
all of the frequencies of operation of DPLL2 can be
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 14
divided to 8 kHz and this will ensure synchronization of
frequencies, from 8kHz upwards, within the two DPLLs.
Both of the DPLLs’ outputs can be connected to
multiplying and filtering APLLs. The outputs of these
APLLs are divided making a number of frequencies
simultaneously available for selection at the output clock
ports. The various combinations of DPLL, APLL and divider
configurations allow for generation of a comprehensive
set of frequencies, as listed in Table 7, “Output Frequency
Selection,” on page 22.
A function is provided to synchronize the lower output
frequencies when DPLL1 is locked to a high frequency
reference input. The dividers that generate the 2 kHz and
8 kHz outputs are reset such that the output 2/8 kHz
clocks are lined up with the input 2 kHz.
The ACS8525 also supports Sync pulse references of
4 kHz or 8 kHz although in these cases frequencies lower
than the Sync pulse reference may not necessarily be in
phase.
The PLL configurations for particular output frequencies is
described in “Output Frequency Selection and PLL
Configuration” on page 22.
PLL Architecture
Figure 5 shows the PLL arrangement in more detail. Each
DPLL comprises a generic Phase and Frequency Detector
(PFD), a Digital Loop filter, and a Digital Timed Oscillator
(DTO- not shown); together with Forward, Feedback, and
Low Frequency (LF) (DPLL1 only) Digital Frequency
Synthesis (DFS) blocks. The DPLL architecture for DPLL1.
is actually more complex than that of DPLL2, and provides
greater functionality.
The selected SEC input is always supplied to DPLL1.
DPLL1 may use either digital feedback or analog
feedback (via APLL3).
DPLL2 always takes its feed from DPLL1 and cannot be
used to select a different input to that of DPLL1, except in
the case where the device is being used to measure
phase difference between input sources. In this case, the
PFD of DPLL2 is used for phase measurement and the
DPLL2 normal output is rendered unusable.
DPLL1 and APLLs
DPLL1 always produces 77.76 MHz regardless of either
the reference frequency (frequency at the input pin of the
device) or the locking frequency (frequency at the input of
the DPLL PFD).
ACS8525 LC/P
DATASHEET
www.semtech.com