ACS8525T Semtech, ACS8525T Datasheet - Page 94

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
2k_8k_from_
DPLL2
Register Name
Indep_FrSync/
MFrSync
Bit No.
Bit No.
Bit 7
Bit 7
1
0
7
7A (cont...)
7B
cnfg_sync_pulses
Description
2k_invert
Register bit to invert the 2 kHz output from
MFrSync.
2k_pulse
Register bit to enable the 2 kHz output from
MFrSync to be either pulsed or 50:50 duty cycle.
Output O2 must be enabled to use “pulsed output”
mode on the MFrSync output, and then the pulse
width on the MFrSync output will be equal to the
period of the output programmed on O2.
cnfg_sync_phase
Sync_OC-N_
rates
Description
Indep_FrSync/MrSync
This allows the option of either maintaining
alignment of FrSync and other clock outputs during
synchronisation from the selected Sync input, or
whether to not maintain alignment to all clocks and
so not disturb any of the output clocks.
Bit 6
Bit 6
Bit 5
Bit 5
Sync_phase_SYNC3
Description
Description
Bit 4
Bit 4
FINAL
Page 94
(R/W) Register to configure the
Sync outputs available from
FrSync and MFrSync and select
the source for the 2 kHz and
8 kHz outputs from O1 and O2.
8k_invert
(R/W) Register to configure the
behaviour of the synchronisation
for the external frame reference.
Bit Value
Bit Value
Bit 3
Bit 3
Sync_phase_SYNC2
0
1
0
1
0
1
8k_pulse
Value Description
2 kHz MFrSync output not inverted.
2 kHz MFrSync output inverted.
2 kHz MFrSync output not pulsed.
2 kHz MFrSync output pulsed.
Value Description
MFrSync & FrSync outputs are always aligned with
other output clocks.
MFrSync & FrSync outputs are independent of other
output clocks.
Bit 2
Bit 2
Default Value
2k_invert
Default Value
ACS8525 LC/P
Bit 1
Bit 1
Sync_phase_SYNC1
DATASHEET
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0000 0000
2k_pulse
0000 0000
Bit 0
Bit 0