ACS8525T Semtech, ACS8525T Datasheet - Page 87
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ACS8525T
Manufacturer Part Number
ACS8525T
Description
Line Card Protection Switch for SONET/SDH Systems
Manufacturer
Semtech
Datasheet
1.ACS8525T.pdf
(112 pages)
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ACS8525T
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Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[7:0]
Bit 7
[7:6]
71
72
cnfg_phase_offset
[15:8]
Description
phase_offset_value[15:8]
Register forming part of the phase offset control. If
the phase offset register is written to when the DPLL
is locked to an input, then it is possible that some
internal signals become out of synchronisation. In
order to avoid this, the phase offset is automatically
“ramped” to the new value. If the phase offset is
only ever adjusted when the device is in Holdover,
then this is not necessary, and this automatic
“ramping” can be disabled, see Reg. 7C,
cnfg_sync_monitor.
This register is ignored and has no affect when
Phase Build-out is enabled in either Reg. 48 or
Reg. 76.
cnfg_PBO_phase_offset
Description
Not used.
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
phase_offset_value[15:8]
Bit 4
Bit 4
FINAL
Page 87
(R/W) Bits [15:8] of the phase
offset control register.
(R/W) Register to offset the mean
time error of Phase Build-out
events.
Bit Value
Bit Value
Bit 3
Bit 3
-
PBO_phase_offset
-
Value Description
The value in this register is to be concatenated with
the contents of Reg. 70 cnfg_phase_offset[7:0].
This value is a 16-bit 2’s complement signed
number. The value multiplied by 6.279 represents
the extent of the applied phase offset in
picoseconds.
The phase offset register is not a control to a
“traditional” delay line. This number 6.279 actually
represents a fractional portion of the period of an
internal 77.76 MHz cycle and can, therefore, be
represented more accurately as follows. Each bit
value of the register represents the period of the
internal 77.76 MHz clock divided by 2
If, for example, the DPLL is locked to a reference
that is +1 ppm in frequency with respect to a perfect
oscillator, then the period, and hence the phase
offset, will be decreased by 1 ppm. Programming a
value of 1024 into the phase offset register will
produce a complete inversion of the 77.76 MHz
output clock.
Note...The exact period of the internal 77.76 MHz
clock is determined by the current state of the DPLL
i.e. in Locked mode its accuracy depends on that of
the locked to input, in Holdover or Free-run it
depends on the accuracy of the external oscillator.
Value Description
-
Bit 2
Bit 2
Default Value
Default Value
ACS8525 LC/P
Bit 1
Bit 1
DATASHEET
www.semtech.com
0000 0000
0000 0000
11
.
Bit 0
Bit 0
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