IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 12

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

Parallel microprocessor Interface
using the parallel microprocessor interface mode.
TABLE 7 – PARALLEL MICROPROCESSOR INTERFACE
TABLE 8 – SERIAL MICROPROCESSOR INTERFACE (SERIAL PERIPHERAL INTERFACE MODE)
interface mode.
TABLE 9 – MISCELLANEOUS
NOTE
1. Inputs with internal pull-ups do not need external pull-ups unless connected to PCB trace (except TRSTB).
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
The Parallel microprocessor interface is configurable to work in Intel or Motorola modes. Be sure to connect SPI_EN to a logic low when
MPM
CSB
RDB
WRB
ADD[5:0]
DBUS[7:0]
INTB
SPI_EN
Four Pins Multiplexed with Parallel microprocessor Pins. Be sure to connect SPI_EN to a logic high when using the serial microprocessor
Name
SDI
SDO
CSB
SCLK
INTB
SPI_EN
REF_CLK
OCLK[3:0]
CLK_SEL[3:0] I-PU CMOS
TIMEBASE
GPIO[4:0]
TDI
TDO
TCK
TMS
TRSTB
RESETB
:
Name
Name
B-PU CMOS
I-ST CMOS
I-ST CMOS
I-ST CMOS
I-PU CMOS
OD CMOS
I/O type
B-PU CMOS Data bus
B-PU CMOS
B-PU CMOS
I-PU CMOS Microprocessor mode: 0=Motorola Mode, 1=Intel mode (sampled after reset)
I-PU CMOS Address bus
I-PU CMOS Logic low selects parallel microprocessor interface (internally pulled up, sampled after reset)
I-PU CMOS
I-PU CMOS
I-PU CMOS
I-PD CMOS
I-ST CMOS Chip select; active low
I-ST CMOS RDB: Read control, active low (in Intel mode), or
I-ST CMOS WRB: Write control; active low; (in Intel mode), or
I-ST CMOS
I-ST CMOS
O-Z CMOS
OD CMOS
O LVTTL
I/O type
I/O type
Parallel microprocessor
DSB: Data strobe, active low (in Motorola mode)
R/WB: Read/write control; when high, read is active; when low, write is active; (in Motorola mode)
Interrupt, active low, open drain
Master clock input
Clock outputs that can be used for SPI-3, phase-shifted to avoid simultaneously switching outputs
Clock select inputs for internal PLL, internal MCLK, and OCLK[3:0] outputs
Timeout signal for counters
General purpose I/O or internal state monitor pins
JTAG data in (internally pulled up)
JTAG data out
JTAG clock
JTAG mode (internally pulled up)
JTAG reset, active low (internally pulled up). Pull down for normal operation.
Master hardware reset, active low
pin used
DBUS[0]
----------
----------
WRB
RDB
CSB
Serial data in, rise edge sampling
Serial data out, falling edge driving
Chip select, active low. SDO is tri-stated when CSB is high
Input clock
Interrupt, active low, open drain
Dedicated input. High selects SPI microprocessor interface (internally pulled up)
Serial Peripheral Interface Pin Use Description
12
Description
Description
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006