IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 8

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

TYPICAL APPLICATION
Exchange between optical ports and NPU/Traffic Manager
1. INTRODUCTION
in optical line cards, Ethernet transport, and multi-service switches. The SPI-
3 and SPI-4 interfaces are defined by the Optical Interworking Forum.
device between network processor units, multi-gigabit framers and PHYs, and
switch fabric interface devices.
DATA PATH OVERVIEW
the device.
the SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to SPI-3 egress
path. SPI-3 and SPI-4 burst sizes are separately configurable.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
The IDT88P8341 device is a SPI-3 to SPI-4 exchange intended for use
The device can be used as a rate adapter, a switch, or an aggregation
Figure 1. Data Path Diagram shows an overview of the data path through
In normal operation, there are two paths through the IDT88P8341 device:
OC-48/
4xOC-12/
16xOC-3
Multi-Rate
SONET
Framer
SPI-3
Figure 1. Typical application: optical port and NPU/Traffic Manager
I/F
SPI-3
SPI-3 ingress to SPI-4 egress
SPI-4 ingress to SPI-3 egress
Memory
IDT88P8341
Figure 2. Data Path Diagram
8
3 interface and are received by the SPI-3 interface block. The fragments are
mapped to a SPI-4 address and stored in memory allocated at the SPI-3 level
until such a time that the Packet Fragment Processor determines that they are to
be transmitted on the SPI-4 interface. The data is transferred in bursts, in line with
the OIF SPI-4 implementation agreement, to the SPI-4 interface block, and are
transmitted on the SPI-4 interface.
interface and are received by the SPI-4 interface block. The SPI-4 address is
translated to a SPI-3 address, and the data contained in the bursts are stored
in memory allocated at the SPI-3 level until such a time that the Packet Fragment
Processor determines that they are to be transmitted on the SPI-3 interface. The
data is transferred in packet fragments, in line with the OIF SPI-3 implementation
agreement, to the SPI-3 interface block, and are transmitted on the SPI-3
interface.
In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the SPI-
In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-4
6372 drw02
SPI-4
I/F
6372 drw03
SPI-4
INDUSTRIAL TEMPERATURE RANGE
NPU
Processor
Control
PCI
APRIL 10, 2006