IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 71

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

according to the calendar sequence.
9.4.7 Common module block base 0x0600 registers
SPI-4 egress calendar_1 (Block_base 0x0600 +
Register_offset 0x00 – 0xFF)
TABLE 103 - SPI-4 EGRESS CALENDAR_1
(256 LOCATIONS)
write access. When the SPI-4 egress calendar_1 is selected, calendar_1 is in
use. There are 256 entries in the SPI-4 egress calendar_1 to schedule the
updating of the FIFO status channel LPs to the attached device. If less than the
maximum 256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate of
the OC-48 channels would benefit from more frequent FIFO status channel
updates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 and
the attached devices must have identical calendars.
according to the calendar sequence.
9.4.8 Common module block base 0x0700 registers
SPI-4 egress configuration register_0 (Block_base
0x0700 + Register_offset 0x00)
TABLE 104 – SPI-4 EGRESS CONFIGURATION
REGISTER_0 (REGISTER_OFFSET 0x00)
read and write access.
4 egress interface. The bit fields of the SPI-4 egress configuration register_0 are
described.
the E_CLK_EDGE field.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
LP
The SPI-4 egress calendar_1 is at Block_base 0x0600 and had read and
LP
The SPI-4 egress configuration register_0 is at Block_base 0x0700 and has
The SPI-4 egress configuration register_0 is used to set the state of the SPI-
E_CLK_EDGE The SPI-4 egress clock active clock edge is selected using
LP
Reserved
E_CLK_EDGE
E_DSC
E_INSYNC_THR
E_OUTSYNC_THR
E_CSW_EN
Reserved
E_LOW
NOSTAT
Field
Field
The LP value programmed schedules a status channel update
The LP value programmed schedules a status channel update
0=SPI-4 egress clock uses the rising clock edge
1=SPI-4 egress clock uses the falling clock edge
13:10
Bits
Bits
7:0
2:0
9:5
14
15
16
17
3
4
Length
Length
8
3
1
1
5
4
1
1
1
1
Initial Value
Initial Value
0x1F
0xFF
0xF
0
0
0
0
0
1
0
71
egress data lines.
old is controlled using the E_INSYNC_THR field. It is recommended to use the
initial value.
threshold is controlled using the E_OUTSYNC_THR field. It is recommended
to use the initial value.
the switching of the active calendars following the reception of the calendar
selection word on the status channel. It is recommended to use the initial value.
range.
NOSTAT is set, the status channel is ignored. There is no DIP-2 error checking,
and no status channel updating. The received status is fixed to starving. The
data channel is put into the IN_SYNCH state.
SPI-4 egress configuration register_1 (Block_base
0x0700 + Register_offset 0x01)
TABLE 105 - SPI-4 EGRESS CONFIGURATION
REGISTER_1 (REGISTER_OFFSET 0x01)
read and write access.
4 egress FIFO status path interface. The bit fields of the SPI-4 egress
configuration register_1 are described.
time interval between scheduling of training sequences on the egress data path
interface. The purpose of the data training interval is to allow the de-skewing
of plus or minus one bit time on the egress data interface if needed. The time is
set for the DATA_MAX_T field multiplied by 128 cycles.
data training sequence that must be scheduled every DATA_MAX_T cycles.
The value for alpha used is actually one more than the ALPHA value
programmed into the ALPHA field.
E_DSC
E_INSYNC_THR
E_OUTSYNC_THR
E_CSW_EN
E_LOW
NOSTAT
The SPI-4 egress configuration register_1 is at Block_base 0x0700 and has
The SPI-4 egress configuration register_1 is used to set the state of the SPI-
DATA_MAX_T
ALPHA
DATA_MAX_T
ALPHA
Field
0=Data de-skewing is disabled
1=Data de-skewing is enabled (recommended setting)
0=Egress calendar switch is disabled. Only SPI-4 egress calen-
dar_0 is used.
1=Egress calendar switch is enabled. Calendar_0 or calendar_1
will be used.
0=SPI-4 egress clock is greater than or equal to 200 MHz
1=SPI-4 egress clock is less than 200 MHz
0=Normal status channel operation
1=No status channel option is selected
The E_DSC bit enables or disables de-skewing of the SPI-4
The E_LOW field selects the SPI-4 egress clock frequency
The SPI-4 egress ALPHA field is the number of repetitions of the
The NOSTAT bit enables the no status channel option. Once
The ingress calendar switch enable bit is used to enable
The SPI-4 egress DATA_MAX_T field is the maximum
The SPI-4 egress DIP-2 in-synchronization thresh-
The SPI-4 egress DIP-2 out-of-synchronization
31:24
Bits
23:0
INDUSTRIAL TEMPERATURE RANGE
Length
24
8
APRIL 10, 2006
Initial Value
0
0