IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 23

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

4. DATAPATH AND FLOW CONTROL
datapaths shown are as follows:
SPI-3 interface can operate in a PHY or Link mode. Refer to Figure 11, Definition
of Data Flows for the main data flows in the device. Logical data flows are
transported over the physical ports. The logical flows are identified by logical
port addresses on the physical port and by a Link identification (LID) map in the
core of the IDT88P8341.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
The following sections describe the datapaths through the device. The
- SPI-3A <-> SPI-4
- SPI-3A <-> microprocessor interface
- SPI-4 <-> microprocessor interface
Where <-> indicates a bidirectional data path.
The IDT88P8341 supports one SPI-3 interface and one SPI-4 interface. The
SPI-3 physical port
SPI-3 ingress
SPI-3 egress
from SPI-3
to SPI-3
Figure 11. Definition of data flows
SPI-4 insert
SPI-4 extract
SPI-4-3 path
23
SPI-3-4 path
DATA BUFFER ALLOCATION
has 128 KByte of on chip memory per direction – a total of 256 KByte of on-chip
data memory.
segments are controlled by a packet fragment processor. The user configures
the maximum number of segments per LP to allocate to a port and the number
of segments allocated from the buffer segment pool that will trigger the flow control
mechanism. There is no limitation on the reallocation of freed segments among
logical ports, as would be present if the memory had been allocated by a simple
address mechanism.
Flexibility has been provided to the user for data buffer allocation. The device
The 128 KByte SPI-3 buffers are divided into 256 byte segments. The
SPI-3 extract
SPI-3 insert
SPI-4 egress
SPI-4 ingress
to SPI-4
from SPI-4
INDUSTRIAL TEMPERATURE RANGE
6372 drw12
SPI-4
physical
port
APRIL 10, 2006