IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 95

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IDT88P8341

Manufacturer Part Number
IDT88P8341
Description
Spi Exchange Spi-3 To Spi-4
Manufacturer
Integrated Device Technology
Datasheet

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14. DATASHEET DOCUMENT REVISION HISTORY
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
ISSUE
0.91
0.92
0.93
0.94
0.95
0.96
0.7
0.8
0.9
1.0
05/21/04
10/01/04
03/01/05
05/09/05
08/05/05
10/20/05
11/09/05
12/01/05
01/05/06
04/10/06
DATE
SPI4_I_STAT_P[0] on Pin name/ball location table (Table 12.2) on page 88.
General Release
AG30 ball location changed to SPI4_I_STAT_N[1] and AF31 ball location changed to
Updated Chip Configuration Sequence (p. 40)
Update Table 27: “Indirect Access Address Register” (p. 45)
Updated Direct Access Registers (p. 47-48)
Updated Common Module Indirect Registers (p. 64)
Updated Electrical and Thermal Specification (p. 75) (the section name changed from Electrical
Characteristics to Electrical and Thermal Specification). Updated JTAG Instructions.
Added Document Revision History (p. 93)
Added sections System Reset and Power on Sequence (p.40).
Updated PFR to PFP in Table 49: "Module A indirect register" (p.53)
Updated Table 80: "SPI-4 ingress packet length configuration" (p.63)
Added Green to Ordering information (p.94)
Updated Table 128: "Absolute maximum ratings" (p.76)
Updated Table 7: "Parallel microprocessor interface" (p.12)
Updated Table 131: "Thermal Characteristics" (p.77)
Updated Microprocessor parallel port section (p.82-85)
Updated Table 126: "Version number register (register_offset 0x30)" (p.75)
Updated 8.2.5 SPI-4 status channel software (p.42)
section (p.26)
Updated Section 8.2.5 "SPI-4 status channel software" (p.42)
Updated 9.3 section title: "Indirect registers for SPI-3A module" (p.53)
Updated Table 127: "Absolute maximum ratings" (p.76)
Updated Table 129: "Terminal Capacitance" (p.77)
Initial Release of Final Datasheet with new section 8.2.7 "Software Eye-Opening Check on SPI-4"
Updated Table 132: SPI-3 AC Input/Output timing specifications (pg. 80)
Update Table 21: “BIT Order Within a 16-BIT Address Register” (p. 44)
Updated length for Reserved in Table 83: "SPI-4 ingress port descriptor" (p.63)
Updated Table 87: "SPI-4 ingress LP to LID map" (p.66)
Updated Figure 4: "PHY mode SPI-3 ingress interface" (p.14)
Deleted Table 13: "NR_LID Field Encoding". Updated SPI-4 egress queues, Normal operation
Updated Table 26 title: "Indirect access address register at 0x34 to 0x35" (p.46)
& new Figure 32. "DDR interface and eye opening check through over sampling" (p.43-44)
Updated Clock generator (pg. 38)
Updated SPI-4 ingress watermark register (pg. 69)
Updated Clock generator control register (pg. 75)
Updated Table 130: Thermal Characteristics (pg. 78)
Updated Table 136: OCLK[3:0] outputs and MCLK internal clock (pg. 82)
DESCRIPTION
95
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006

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