IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 43

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

example, a SPI-4 clock of 400 MHz gives a data unit interval of 1.25 ns, so match
the lengths within the entire signal group to within 625 ps, or 3 inches.
minimum trace spacing possible while still being able to get 100 ohms differential
impedance (tightly edge-coupled pair routing).
an inner layer, referencing ground planes). For example, 7 mil wide 1/2 oz
copper traces separated by 10 mils, with 10 mil dielectric spacing to ground
planes above and below the traces gives 100 Ohms of differential impedance
for FR-4 with a relative dielectric constant (ε
spacing between adjacent differential pair traces is 20 mils, crosstalk is 0.6% for
signals terminated to within a 10% impedance match. If the edge to edge spacing
between a differential pair and an LVTTL signal is 30 mils within the parameters
of this example, crosstalk is 0.8% (with the LVTTL signals series terminated).
Use a field solver for more accurate results.
signals.
GENERAL LAYOUT GUIDELINES
thickness to the reference plane (or three times the trace separation, whichever
is greater) in separation width, to minimize the crosstalk contribution of noise on
the LVDS signals from the noisy LVTTL environment.
(or twice the trace separation, whichever is greater) to the reference plane to
reduce crosstalk.
from either side of the trace and be unbroken.
a frequency of 10 times SPI-4 clock to over-sample the data on a lane. For each
sampling clock cycle t position n data are sampled and labeled as R
following operation is then performed:
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
3) Keep P and N signals within a differential pair on the same layer with the
4) Route all differential pairs as 100 Ohm embedded differential stripline (on
5) Follow the SPI-3 layout guidelines for any routed SPI-4 LVTTL status
1) Keep LVDS signals far from LVTTL signals: at least three times the dielectric
2) Separate signals of the same type by at least twice the dielectric thickness
3) The reference planes must extend at least five times the dielectric thickness
Refer to the IDT88P8342 uses an internal sampling clock cycle which has
over sample
position
counter
clock
Figure new32. DDR interface and eye opening check through over sampling
data
R
or D
0 1 2 3 4 5 6 7 8 9 a b c
K
) of 4.2. If the edge to edge
d
n
c
0
c
1
c
2
t
.d
c
3
n
. The
c
d
4
n+1
43
c
5
should share the same reference (such as ground), connected by reference
vias close to the signal vias for good current return. If a different reference plane
(such as Vcc) must be used due to a signal layer change, good high-frequency
0.01 µF ceramic capacitors must be used to connect the references together
as close to the signal vias as possible to ensure good transmission line properties
and current return.
source for REF_CLK is important. If I_DCLK is used instead of REF_CLK,
ensure that I_DCLK is low in jitter and always available.
pins, using at least 15 mil traces and double vias for reduced inductance where
possible.
frequency decoupling and to lower the power-supply impedance.
RESETB for normal operation.
noisy digital environment. Use ferrite beads and capacitors (Pi filters) for
VDDA18_x and VDDA33.
8.2.7 Software Eye-Opening Check on SPI-4
Interface
are used to update or sink data.
CNT
CNT
CNT
CNT
CNT
CNT
CNT
CNT
CNT
c
6
4) Avoid changing layers on high-speed signals. On a layer change, signals
5) Use of a low-jitter (100 picoseconds peak-peak maximum jitter) frequency
6) Keep the power decoupling capacitors as close as possible to the power
7) Distribute some large-valued capacitors around the board for low-
8) TRSTB (JTAG reset) must have a pull down resistor or be connected to
9) Filter the 1.8 Volt and 3.3 Volt analog power pins to isolate them from the
10) Suppress non-functional inner layer pads.
Since the SPI-4 interface is a DDR interface, both rising and falling edges
c
0
1
2
3
4
5
6
7
9
7
= R
= R
= R
= R
= R
= R
= R
= R
= R
c
8
t
t
t
t
t
t
t
t
t+1
.d
.d
.d
.d
.d
.d
.d
.d
.d
2
3
4
5
6
7
8
9
c
^ R
^ R
^ R
^ R
^ R
^ R
^ R
^ R
9
0
^ R
t
t
t
t
t
t
t
t+1
.d
.d
.d
.d
.d
.d
.d
t+1
.d
3
4
5
6
7
8
9
.d
0
1
INDUSTRIAL TEMPERATURE RANGE
6372 drw23b
APRIL 10, 2006