MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 114

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

RFS bit of SCSR register
RDR status bit/interrupt
Hardware Functional Description
The receiver timing for an 8-bit word with continuous clock, FIFO disabled, five words per frame sync, in
network mode is shown in Figure 75. The explanatory notes for the receive portion of the figure are shown
in Table 57.
114
Note
internal word clock
1
2
3
4
5
Continuous SRCK
Valid
3. Enable RXFIFO (RFEN=1) and configure receive watermark (RFWM=n) if RXFIFO is
4. Enable receive interrupts.
5. Set the RE bit (RE = 1) to enable the receiver operation on the next frame sync boundary.
RXSR register
SRX register
used.
Source
register
Signal
SRCK
SRXD
RXSR
SRFS
time-slot
SRXD
SRFS
SRX register
Destination
register
Signal
RXSR
Invalid
Table 57. Notes for Receive Timing in Figure 75
Freescale Semiconductor, Inc.
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For More Information On This Product,
Figure 75. Network Mode Receive Timing
MC72000 Advance Information Data Sheet
Example of a 5 time-slot frame, receiving data from time-slots 0 and 2. Note that
the receive hardware will obtain data on the SRXD pin every bit time. The software
must determine which data belongs to each time-slot and discard the unwanted
time-slot data.
The figure shows the transmit and receive timing as the same, although this is not
the general case.
Example with bit-length frame sync and standard timing (RFSI=0, RFSL=1,
REFS=0). Frame timing begins with the rising edge of SRFS.
Data on the SRXD pin is sampled on the falling edge of SRCK and shifted into the
RXSR register.
At the word clock, the data in the RXSR register is transferred to the SRX register.
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Indefinite transition depends on SW interrupt processing
Preliminary
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6
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Description
5
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10
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MOTOROLA
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