MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 70

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Reset
Reset
W
R
Hardware Functional Description
7.3.7.4 Interrupt Control/Status Register (INTREG)
INTREG is a 32-bit register. The high 16 bits are reserved bits and are always read as 0.
TE—TXFIFO Empty Status
TH—TXFIFO Half Status
TF—TXFIFO Full Status
RR—RXFIFO Data Ready Status.
RH—RXFIFO Half Status
RF—RXFIFO Full Status
70
BOEN
The TE bit is forced to 0 when the SPIEN is zero and will change to 1 after SPIEN is set.
The TH bit is forced to 0 when the SPIEN is zero and will change to 1 after SPIEN is set.
31
15
0
0
1 = The TXFIFO is empty but data shifting may still be on-going
0 = At least one data word is in the TXFIFO
1 = More than or equal to 4 empty slots in the TXFIFO
0 = Less than 4 empty slots in the TXFIFO
1 = 8 data words in the TXFIFO
0 = Less than 8 data words in the TXFIFO
1 = At least one data word is ready in the RXFIFO
0 = The RXFIFO is empty
1 = More than or equal to 4 data words in the RXFIFO
0 = Less than 4 data words in the RXFIFO
1 = 8 data words in the RXFIFO
0 = Less than 8 data words in the RXFIFO
ROEN
30
14
0
0
= Unimplemented or Reserved
To make sure no data transaction is on-going, read the XCH bit in the CONTROLREG.
RFEN
29
13
0
0
RHEN
Figure 39. Interrupt Control/Status Register (INTREG)
28
12
0
0
Table 32. BITCOUNT[3:0] Encoding (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
RREN
27
11
0
0
BITCOUNT[3:0]
TFEN
Register address: Base + 0x0C
26
10
0
0
Go to: www.freescale.com
0001
1110
1111
.
.
.
THEN
25
0
9
0
Preliminary
TEEN
24
Reserved
0
8
0
15-bit transfer
16-bit transfer
2-bit transfer
BO
23
0
7
0
Function
.
.
.
RO
22
0
6
0
21
RF
0
5
0
RH
20
0
4
0
RR
19
0
3
0
18
TF
0
2
0
MOTOROLA
17
TH
0
1
0
16
TE
0
0
0