MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 89

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

RESET:
7.4.5.2.8
The SCSR is a 16-bit register used to set up and monitor the SSI. The top half of the register (bits [15:8]) is
the read/write portion and is used for SSI setup. The bottom half of the register (bits [7:0]) is read-only and
is used to interrogate the status and serial input flags of the SSI. The control and status bits are described in
the following paragraphs.
DIV4DIS—Divider 4 Disable
RSHFD—Receive Shift Direction
MOTOROLA
W
R
The bit clock output is also available internally for use as the bit clock to shift the transmit and receive
shift registers. Careful choice of the crystal oscillator frequency and the prescaler modulus allows the
telecommunication industry standard CODEC master clock frequencies of 2.048 MHz, 1.544 MHz, and
1.536 MHz to be generated. For example, a 24.576 MHz clock frequency can be used to generate the
standard 2.048 MHz and 1.536 MHz rates, and a 24.704 MHz clock frequency can be used to generate
the standard 1.544 MHz rate. Table 41 gives examples of PM[7:0] values that can be used in order to
generate different bit clocks.
This bit controls whether the MSB or LSB is received first for the receive section. If the RSHFD bit is
cleared, data is received MSB first. If the RSHFD bit is set, the LSB is received first.
DIV4D
1 = FIX_CLK is equal to IP_CLK
0 = FIX_CLK = IP_CLK/4 for both transmitter and receiver clock generator circuits
15
IS
0
Table 41. SSI Bit Clock as a Function of Peripheral Clock and Prescale Modulus
IPG_CLK (MHz)
DIV4DIS = 1
RSH-
FD
14
= Unimplemented or Reserved
0
SSI Control/Status Register (SCSR)
SSI Status flag is updated when SSI is enabled.
All the flags in the status portion of the SCSR are updated after the first bit
of the next SSI word has completed transmission or reception. Some status
bits (ROE and TUE) are cleared by reading the SCSR followed by a read
or write to either the SRX or STX register.
32
24
16
12
RSC
KP
13
0
MAE
Freescale Semiconductor, Inc.
RD-
12
0
FIX_CLK/4 (MHz)
For More Information On This Product,
MC72000 Advance Information Data Sheet
Max Bit Clock,
Figure 59. SCSR Register Diagram
MAE
TD-
11
0
8
6
4
3
Go to: www.freescale.com
RFSI
10
0
RFS
Base + 0x04
Preliminary
9
L
0
NOTE:
NOTE:
2.048
MHz
REF
—
1
2
S
8
0
PM[7:0] Values For Different SCK
RDR
7
0
1.544
MHz
—
—
4
TDE
6
0
Hardware Functional Description
ROE
(PSR=0)
512 kHz
5
0
16
12
8
6
TUE
4
0
TFS
(PSR=0)
3
0
64 kHz
128
96
64
48
RFS
2
0
RFF
1
0
89
TFE
0
0