MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 53

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

7.2.4 General UART Definitions
These general UART definitions will help in understanding the following sections.
MOTOROLA
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Start Bit — A start bit is a bit of logic zero which indicates the beginning of a data frame. A start
bit must begin with a one to zero transition and is preceded by at least one bit time of logic one.
Stop Bit — A stop bit is a bit of logic one which indicates the end of a data frame. A stop bit follows
the data and any parity bit. They mark the end of a unit of transmission (normally a byte or
character).
Break — A frame or longer with RX/TX held low at logic zero. This kind of frame is generally sent
to signal the end of a message or the beginning of a new message.
Frame — A frame consists of a start bit followed by a specified number of data or information bits
terminated by a stop bit. The number of data or information bits depends on the format specified
and must agree between the transmitting device and the receiving device. The most common frame
format is one start bit followed by eight data bits (LSB first) terminated by one stop bit.
Framing Error — An error condition in which the stop bit of the received frame was missing. A
framing error results when the frame boundaries in the received bit stream are not synchronized
with the receiver bit counter. Framing errors are not always detected: if a data bit in the expected
stop bit time happens to be a logic one, the framing error may go undetected. A framing error is
always present on the receiver side, when the transmitter is sending breaks. However, if the UART
is set up to expect two stop bits, and only the first stop bit is received, then this is not a framing error.
Parity Error — An error condition in which the calculated parity of the received data bits in the
frame is different from the parity bit received on the RXD line. Parity error is only calculated after
an entire frame is received.An additional stop bit and parity bit may also be included.
1.
2.
3.
Baud Rate
1,843,200
115,200
230,400
460,800
921,600
19,200
28,800
38,400
57,600
1,200
2,400
4,800
9,600
Fractional divider values are shown for the 16 times oversampling mode.
At this baud rate, only 8 x oversampling is possible because (12 MHz/921600) < 16.
At this baud rate, only 8 x oversampling is possible because (24 MHz/1843200) < 16.
Freescale Semiconductor, Inc.
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
MOD
For More Information On This Product,
MC72000 Advance Information Data Sheet
Table 26. Standard Baud Rates
IPSCLK = 12 Mhz
Go to: www.freescale.com
6143
1535
3071
6143
INC
127
255
383
511
767
15
31
63
—
2
Preliminary
115,200
230,400
460,800
921,600
19,200
28,800
38,400
57,600
FREQ
1,200
2,400
4,800
9,600
—
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
14000
MOD
IPSCLK = 24 Mhz
1
Hardware Functional Description
8601
1,535
3,071
6,143
INC
127
191
255
383
767
15
31
63
7
3
1843285.7
115,200
230,400
460,800
921600
19,200
28,800
38,400
57,600
FREQ
1,200
2,400
4,800
9,600
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