MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 120

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Hardware Functional Description
The bit clock is used to serially clock the data. It is visible on the serial transmit clock (STCK) and serial
receive clock (SRCK) pins. The word clock is an internal clock used to determine when transmission of an
8-, 10-, 12-, or 16-bit word has completed. The word clock in turn then clocks the frame clock, which marks
the beginning of each frame. The frame clock can be viewed on the STFS and SRFS pins. The bit clock can
be received from an SSI clock pin or can be generated from the peripheral clock passed through a divider,
as shown in Figure 81.
7.4.8.1 Description of Clock Operation
The following section describes clock operation.
7.4.8.1.1
Data clock and frame sync signals can be generated internally by the SSI or can be obtained from external
sources. If internally generated, the SSI clock generator is used to derive bit clock and frame sync signals
120
WORD_CLOCK
Clock
SRCK
STCK
SRFS
STFS
•
•
•
STCK, SRCK
STFS, SRFS
Bit clock—Used to serially clock the data bits in and out of the SSI port.
Word clock—Used to count the number of data bits per word (8, 10, 12, or 16 bits).
Frame clock—Used to count the number of words in a frame.
data
Serial Bit Clock
(STCK, SRCK)
Priority
SSI Clock and Frame Sync Generation
Figure 79. SSI Clocking (8-bit words, 3 time-slots/frame)
TS0
Internal/External
Internal/External
Internal/External
Internal/External
Freescale Semiconductor, Inc.
Source
For More Information On This Product,
MC72000 Advance Information Data Sheet
(/8, /10, /12, /16)
Word Divider
Frame n
Figure 80. SSI Clock Generation
TS1
Table 61. Clock Summary
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Transmit data is changed on the rising edge of this clock. The TSCKP
bit of the SCR2 register can invert the clock if needed.
Receive data is captured on the falling edge of this clock. The RSCKP
bit of the SCSR register can invert the clock if needed.
Transmit frames begin with the rising edge of this signal. See the
definition of the TEFS bit of the SCR2 register for timing options. The
TFSI bit can invert this signal if needed.
Receive frames begin with the rising edge of this signal. See the
definition of the REFS bit of the SCSR register for timing options.
Preliminary
TS2
Word clock
TS0
Frame Divider
Characteristics
(/1 to /32)
Frame n+1
TS1
Frame clock
STFS, SRFS
TS2
MOTOROLA