MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 97

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

TSHFD—Transmit Shift Direction
TSCKP—Transmit Clock Polarity
SSIEN—SSI Enable
NET—Network Mode
TFSI—Transmit Frame Sync Invert
TFSL—Transmit Frame Sync Length
MOTOROLA
Table 44 shows the clock configuration options.
This bit controls whether the MSB or LSB is transmitted first for the transmit section.
This control bit determines which bit clock edge is used to clock out data in the transmit section.
This control bit enables and disables the SSI.
This control bit selects the operational mode of the SSI.
This control bit selects the logic of frame sync I/O.
This control bit selects the length of the frame sync signal to be generated or recognized. See Figure 60
for an example timing diagram of the FS options.
The frame sync is deasserted after one bit for bit length frame sync and after one word for word length
frame sync.
1 = LSB is transmitted first.
0 = Data is transmitted MSB first.
1 = Falling edge of the bit clock is used to clock the data out.
0 = Data is clocked out on the rising edge of the bit clock.
1 = SSI is enabled.
0 = SSI is disabled and held in a reset condition.
1 = Network mode is selected.
0 = Normal mode is selected.
1 = Frame sync is active low.
0 = Frame sync is active high.
1 = A one-clock-bit-long frame sync is selected.
0 = A one-word-long frame sync is selected.
When enabled, causes an output frame sync to be generated when set up for internal frame sync
or causes the SSI to wait for the input frame sync when set up for external frame sync.
When disabled, all output pins are tri-stated, the status register bits are preset to the same state
produced by the power-on reset, and the control register bits are unaffected. The contents of the
STX, TXFIFO, and RXFIFO are cleared when this bit is reset. When SSI is disabled, all internal
clocks are disabled except clocks required for register access. When clearing SSIEN, it is
recommended to also clear RE and TE.
The length of this word-long frame sync is the same as the length of the data word selected by
WL[1:0].
The CODEC device labels the MSB as bit 0, whereas the SSI labels the
LSB as bit 0. Therefore, when using a standard CODEC, the SSI MSB (or
CODEC bit 0) is shifted out first, and the TSHFD bit should be cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
Preliminary
NOTE:
Hardware Functional Description
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