DSP56364D Motorola Inc, DSP56364D Datasheet - Page 12

• Manufacturer Part Number: DSP56364D
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: Motorola Inc

MODD/
Signal/Connection Descriptions
Interrupt and Mode Control
1.6
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
Signal Name
MODA/
MODB/
1-8
RESET
IRQA
IRQB
IRQD
INTERRUPT AND MODE CONTROL
Type
Input
Input
Input
Input
during
Reset
State
Input
Input
Input
Input
Freescale Semiconductor, Inc.
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Table 1-8 Interrupt and Mode Control
Mode Select A/External Interrupt Request A—MODA/
Schmitt-trigger input, internally synchronized to the internal system clock.
MODA/
becomes a level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. MODA, MODB, and MODD
select one of 8 initial chip operating modes, latched into the OMR when the
RESET
system clock, multiple processors can be re synchronized using the WAIT
instruction and asserting
stop standby state and
This input is 5 V tolerant.
Mode Select B/External Interrupt Request B—MODB/
Schmitt-trigger input, internally synchronized to the internal system clock.
MODB/
becomes a level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. MODA, MODB, and MODD
select one of 8 initial chip operating modes, latched into OMR when the
signal is deasserted. If
clock, multiple processors can be re-synchronized using the WAIT instruction
and asserting
This input is 5 V tolerant.
Mode Select D/External Interrupt Request D—MODD/
Schmitt-trigger input, internally synchronized to the internal system clock.
MODD/
becomes a level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. MODA, MODB, and MODD
select one of 8 initial chip operating modes, latched into OMR when the
signal is deasserted. If
clock, multiple processors can be re synchronized using the WAIT instruction
and asserting
This input is 5 V tolerant.
Reset—
is placed in the reset state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a capacitor charging)
to reset the chip reliably. When the
operating mode is latched from the MODA, MODB, and MODD inputs. The
RESET
be supplied before deassertionof
This input is 5 V tolerant.
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IRQA
IRQB
IRQD
RESET
signal is deasserted. If
signal must be asserted during power up. A stable EXTAL signal must
selects the initial chip operating mode during hardware reset and
selects the initial chip operating mode during hardware reset and
IRQB
IRQD
selects the initial chip operating mode during hardware reset and
is an active-low, Schmitt-trigger input. When asserted, the chip
to exit the wait state.
to exit the wait state.
IRQB
IRQD
IRQA
IRQA
Signal Description
is asserted synchronous to the internal system
is asserted, the processor will exit the stop state.
is asserted synchronous to the internal system
to exit the wait state. If the processor is in the
IRQA
RESET
RESET
is asserted synchronous to the internal
.
signal is deasserted, the initial chip
IRQA
IRQB
IRQD
is an active-low
is an active-low
is an active-low
MOTOROLA
RESET
RESET