DSP56364D Motorola Inc, DSP56364D Datasheet - Page 75

• Manufacturer Part Number: DSP56364D
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: Motorola Inc

In I
The programmed serial clock cycle (T
in order to achieve the desired SCL frequency, as shown in
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. T
(F
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $38 (=56).
MOTOROLA
SCL
2
HREQ
C mode, the user may select a value for the programmed serial clock cycle from
SDA
SCL
= 100 KHz (i.e. T
to
6
4096
T
HDM[7:0] = 8930ns / (2 10ns 8) - 1 = 55.8
172
Stop
I
Filters bypassed
Narrow filters enabled
Wide filters enabled
2
CCP
T
173
C
174
188
Start
= 10 s - 2.5 10ns - 45ns - 1000ns = 8930ns
Table 2-19 SCL Serial Clock Cycle generated as Master
T
C
SCL
177
= 10 s), T
Freescale Semiconductor, Inc.
For More Information On This Product,
176
189
171
MSB
DSP56364 Advance Information
(if HDM[5:0] = $02 and HRS = 1)
(if HDM[7:0] = $FF and HRS = 0)
I
179
R
2
T
T
T
CCP
Go to: www.freescale.com
Figure 2-22 I
I
I
I
= 1000ns), with filters bypassed
2
2
2
CCP
CCP
CCP
), SCL rise time (T
C
186
= 10ns), operating in a standard-mode I
+ 2.5
+ 2.5
+ 2.5
178
175
Serial Host Interface (SHI) I
T
T
T
C
C
C
2
C Timing
+ 45ns +
+ 135ns +
+ 223ns +
184
Table
R
182
), and the filters selected should be chosen
180
LSB
2-19.
T
T
T
R
R
R
ACK
187
2
183
C Protocol Timing
2
C environment
Specifications
Stop
AA0275
2-55