DSP56364D Motorola Inc, DSP56364D Datasheet - Page 2

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DSP56364D

Manufacturer Part Number
DSP56364D
Description
24-Bit Audio Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
Overview
Features
1
1.1
2
PERIPHERAL
EXPANSION
AREA
EXTAL
100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
Object Code Compatible with the 56000 core.
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support.
Program Control with position independent code support and instruction cache support.
Six-channel DMA controller.
PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1
to 16) and power saving clock divider (2
Internal address tracing support and OnCE for Hardware/Software debugging.
DATA BUS
GENERATION UNIT
INTERNAL
SWITCH
CLOCK
SIX CHANNELS
PLL
Features
Digital Signal Processing Core
DMA UNIT
ADDRESS
PINIT/NMI
RESET
GPIO
4
INTERRUPT
PROGRAM
CONT
ESAI
Freescale Semiconductor, Inc.
12
For More Information On This Product,
Figure 1 DSP56364 Block Diagram
PROGRAM
MODA/IRQA
MODB/IRQB
MODD/IRQD
DECODE
DSP56300
CONT
DSP56364 Advance Information
CORE
24-BIT
SHI
5
Go to: www.freescale.com
PROGRAM
ADDRESS
GEN
PROGRAM RAM
PROGRAM ROM
i
: i=0 to 7). Reduces clock noise.
Bootstrap ROM
0.5K x 24
192 x 24
8K x 24
DDB
YDB
XDB
PDB
GDB
24 X 24 + 56 56-BIT MAC
DAB
YAB
XAB
PAB
BARREL SHIFTER
ACCUMULATORS
TWO 56-BIT
DATA ALU
MEMORY
1K X 24
RAM
X
24 BITS BUS
MEMORY
1.5K X 24
RAM
Y
DRAM & SRAM
INTERFACE
MEMORY
EXPANSION
AREA
EXTERNAL
ADDRESS BUS
EXTERNAL
DA T A BUS
SWITCH
BUS
SWITCH
POWER
MGMT
OnCE
JTAG
6
18
8
4
ADDRESS
MOTOROLA
CONTROL
DATA

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