DSP56364D Motorola Inc, DSP56364D Datasheet - Page 55

• Manufacturer Part Number: DSP56364D
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: Motorola Inc

No.
192
193
194
195
Notes:
MOTOROLA
No.
157
158
159
160
161
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
RD assertion to data valid
RD deassertion to data
not valid
WR assertion to data
active
WR deassertion to data
high impedance
Random read or write
cycle time
RAS assertion to data valid
(read)
CAS assertion to data valid
(read)
Column address valid to
data valid (read)
CAS deassertion to data
not valid (read hold time)
1.
2.
3.
4.
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
Characteristics
Characteristics
The number of wait states for out of page access is specified in the DCR.
The refresh period is specified in the DCR.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
t
Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See
Figure 2-17
GZ
3
.
).
3
Freescale Semiconductor, Inc.
4
For More Information On This Product,
Symbol
DSP56364 Advance Information
Symbol
t
t
t
t
t
GA
GZ
t
RAC
CAC
Go to: www.freescale.com
t
OFF
RC
AA
0.75
4.75
4.75
2.25
2.25
Expression
Expression
4
3
3
0.25
9
T
T
T
C
T
C
C
T
T
T
T
C
T
C
C
C
C
T
External Memory Expansion Port (Port A)
C
7.5
7.5
6.5
C
0.3
7.5
6.5
7.5
6.5
3
136.4
37.2
Min
Min
0.0
0.0
—
—
—
—
—
—
—
—
20 MHz
66 MHz
192.5
Max
12.5
Max
64.5
26.6
40.0
4
—
—
—
—
—
—
—
112.5
24.7
Min
Min
0.0
0.0
—
—
1, 2
—
—
—
—
—
—
30 MHz
80 MHz
Specifications
(continued)
125.8
1, 2
Max
Max
52.9
21.6
31.0
OFF
8.3
4
—
—
—
—
—
—
—
and not
Unit
2-35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns