DSP56364D Motorola Inc, DSP56364D Datasheet - Page 78

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DSP56364D

Manufacturer Part Number
DSP56364D
Description
24-Bit Audio Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
Notes:
458 FST input (wl) to data out enable from high
459 FST input (wl) to transmitter #0 drive enable
460 FST input (wl) setup time before TXC falling
461 FST input hold time after TXC falling edge
462 Flag output valid after TXC rising edge
463 HCKR/HCKT clock cycle
464 HCKT input rising edge to TXC output
465 HCKR input rising edge to RXC output
No.
Specifications
Enhanced Serial Audio Interface Timing
2-58
impedance
assertion
edge
1.
2.
3.
4.
5.
6.
7.
V
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
i ck s = internal clock, synchronous mode
bl = bit length
wl = word length
wr = word length relative
TXC(SCKT pin) = transmit clock
RXC(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high speed clock
HCKR(HCKR pin) = receive high speed clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the
bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit
length frame sync signal), until the one before last bit clock of the first word in frame.
Periodically sampled and not 100% tested
CC
(asynchronous implies that TXC and RXC are two different clocks)
(synchronous implies that TXC and RXC are the same clock)
= 3.16 V
Table 2-20 Enhanced Serial Audio Interface Timing (continued)
Characteristics
0.16 V; T
Freescale Semiconductor, Inc.
For More Information On This Product,
J
1, 2, 3
= 0°C to +105°C, C
DSP56364 Advance Information
Go to: www.freescale.com
Symbol
L
= 50 pF
Expression
21.0
40.0
Min
2.0
4.0
0.0
Max
27.0
31.0
32.0
18.0
27.5
27.5
MOTOROLA
Cond-i
tion
x ck
x ck
x ck
i ck
i ck
i ck
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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