DSP56364D Motorola Inc, DSP56364D Datasheet - Page 60
![no-image](/images/no-image-200.jpg)
DSP56364D
Manufacturer Part Number
DSP56364D
Description
24-Bit Audio Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
1.DSP56364D.pdf
(162 pages)
- Current page: 60 of 162
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Notes:
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
No.
Specifications
External Memory Expansion Port (Port A)
2-40
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
CAS assertion to WR deassertion
RAS assertion to WR deassertion
WR assertion pulse width
WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion (refresh)
RAS deassertion to CAS assertion (refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
The number of wait states for out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56364.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Either t
RCH
Characteristics
or t
RRH
Freescale Semiconductor, Inc.
must be satisfied for read cycles.
For More Information On This Product,
DSP56364 Advance Information
4
4
Go to: www.freescale.com
Symbol
t
t
t
t
t
t
t
t
t
WCH
WCR
t
RWL
CWL
WCS
ROH
t
t
DHR
CSR
RPC
t
t
WP
DS
DH
GA
GZ
11.75
10.25
11.5
5.75
5.25
7.75
2.75
11.5
0.75
7.5
6.5
1.5
Expression
10
5
0.25
T
T
T
T
T
C
T
T
T
T
T
T
T
C
C
T
T
C
C
C
C
C
C
C
C
C
C
C
T
4.2
7.0
C
4.2
4.3
4.0
4.5
4.0
4.0
4.0
4.0
4.0
0.3
4.3
4.3
3
110.5
113.2
103.2
111.0
45.8
70.8
53.5
48.5
73.5
60.7
11.0
23.5
Min
0.0
7.2
—
—
1, 2
(continued)
OFF
MOTOROLA
Max
93.0
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
and not t
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GZ
.
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