LM3S317-IQN20-A0T Luminary Micro, Inc., LM3S317-IQN20-A0T Datasheet - Page 135

• Manufacturer Part Number: LM3S317-IQN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

May 4, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
GPIO Open Drain Select (GPIOODR)
Offset 0x50C
7:0
RO
RO
31
15
0
0
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 139). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R,
GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts
as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open
drain output when set to 1.
RO
RO
30
14
0
0
reserved
Name
ODE
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
Output Pad Open Drain Enable
0: Open drain configuration is disabled.
1: Open drain configuration is enabled.
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
ODE
R/W
RO
19
0
3
0
LM3S317 Data Sheet
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
135