LM3S317-IQN20-A0T Luminary Micro, Inc., LM3S317-IQN20-A0T Datasheet - Page 339

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LM3S317-IQN20-A0T

Manufacturer Part Number
LM3S317-IQN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
May 4, 2007
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
PWMn Counter (PWMnCOUNT)
RO
RO
31
15
0
0
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054
is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB
registers, see page 342 and 344) or drive an interrupt (via the PWMnINTEN register, see
page 335). A pulse with the same capabilities is generated when this value is zero.
contain the current value of the PWM counter. When this value matches the load register, a pulse
RO
RO
30
14
0
0
reserved
Name
Count
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Count
Description
Reserved bits return an indeterminate value, and should
never be changed.
The current value of the counter.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S317 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
339

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