AN1154 STMicroelectronics, AN1154 Datasheet - Page 34

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

AN1154 - APPLICATION NOTE
M88 FLASH+PSD Chip Simulation
PSDsilosIII is ST's version of SIMUCAD’s SILOSIII simulator software. It provides chip-level simulation
and design verification using the Verilog Hardware Description Language (Verilog-HDL). Appendix B lists
the stimulus file ( tutor8XX.stl ) for this tutorial.
Many of the internal nodes on the M88x3Fxx are available for tracing. Descriptions of the signals that can
be traced by the simulator are listed in Appendix C.
PSDsoft generates all but one of the input files required by the simulator. The file that must be created is
the stimulus file (.stl). In the stimulus file, you can use the same names you used in your PSDabel file, and
the predefined ones in Appendix C.
PSDsoft.run File
One of the files generated by PSDsoft for the simulation process is PSDsoft.run, as listed in Figure 29. It
is a command batch file used by PSDsilosIII. For additional information on the PSDsilosIII commands
(those commands that start with !), please refer to PSDsilosIII’s on-line help.
Figure 29. PSDsoft.run File
In the PSDsoft.run file:
Tutor8XX.top is generated by PSDsoft, based on the PSDabel file, and allows you to use of any of the
signal names within the PSDabel file. There are also parameter definitions for high impedance state
signals (Z1 through Z32) in the .top file. Notice how the “endmodule” statement is the last statement in the
PSDsoft.run file. It is there because it complements the “module WSIdesign” statement in the .top file.
There is one important thing to note about the included library files: these files look for other files
automatically generated by PSDsoft from the fuse-map file, and have a .afu or .pfu extension. They allow
simulation of the logic, defined in the .abl file, in the stimulus file.
Running the Logic Simulator
1. Review the stimulus file ( tutor8XX.stl ) listed in Appendix B.
2. Pull down the PSDsoft menu in the main PSDsoft window and select PSD Simulator, or click the
3. The tutor8XX.stl file is automatically opened in PSDsoft, as shown in Figure 30.
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“`time-scale 1ns/0.1ns” is a compiler directive for defining the delay values for a module
“1 ns” is the unit of measurement for times and delays
“0.1 ns” is the precision to which the delays are rounded off
“`include” is also a compiler directive that allows the entire contents of a Verilog source file to be
included in another file ( PSDsoft.run in this case).
simulator button on the tool bar.
!Reset all
!file .sav = Tutor8XX
!control .ext = all
‘timescale 1ns/0.1ns
!lib d:\psdsoft\psd8.v
‘include "tutor8XX.top"
‘include "tutor8XX.stl"
endmodule