AN1154 STMicroelectronics, AN1154 Datasheet - Page 80

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

AN1154 - APPLICATION NOTE
Figure 65. Final Sys Mem Map for 8031-M8813F1x, move EEPROM to data space
WRITE 0Ch TO THE VM REGISTER
CODE PARTITIONING IN THE FLASH MEMORY PAGES
Ultimately, the MCU will be executing from Flash memory since the EEPROM is used for boot-up and ISP
in this design. Let us assume that we have 128 KBytes of program space in Flash memory, as shown in
Figure 65. The 128 KBytes of code resides in four areas: 32 KBytes in the common area (FS0 and FS1,
accessible from any page), 32 KBytes on page zero (FS2 and FS3), 32 KBytes on page one (FS4 and
FS5), and 32 KBytes on page two (FS6 and FS7).
If the 8031 never leaves page zero while executing, it can access 64 KBytes of Flash memory in FS0
through FS3 as well as all of the SRAM and I/O. If the 8031 execution jumps to Flash memory on pages
one or two from a call on the upper half of page zero (FS2 or FS3), care must be taken to leave a path to
return to page zero again. However, if the call to page one or two is from a routine in the lower half of page
zero (the common area, FS0 or FS1), there is no problem returning from the call.
When placing code in the Flash memory on the upper half of pages zero, one, or two, the software
designer must break tasks into logical groups. These groups should not need to access code frequently
on other pages. (Most software can be split in this manner and is a result of a good modular design.) Since
system SRAM is available on any page, firmware routines that reside on different pages may pass data
using global variables or the stack. The designer can create page-switching algorithms to jump between
tasks on different pages. There are many ways to implement a paging scheme: one method involves the
use of a table that contains addresses and page numbers of all program tasks, which may be called from
page to page. The table and algorithms must reside in the portion of Flash memory that is located in the
common area. This provides a very clean paging solution, which may be implemented using a high-level
compiler. (The compiler from Keil supports this directly, and creates the tables for you.) The only penalty
when using this method is the overhead experienced when switching from one page to another.
For this tutorial design, five different files from an MCU cross-compiler and linker are used to program the
NVM sections of the M8813F1x. These are dummy files with no code in them, but are present to illustrate
the merging of MCU firmware with the PSD configuration during the Address Translate operation. If this
were a real design, the file common.hex would contain all of the common functions and interrupt vectors,
and would be programmed into FS0/FS1. Three more files from the MCU linker, page_0.hex, page_1.hex,
and page_2.hex would contain the partitioned code described above. As such, these three files would be
programmed into segments FS2/FS3, FS4/FS5, and FS6/FS7, respectively. Finally, the file boot.hex ,
80/83
ACROSS ALL
PROGRAM
COMMON
MEMORY
PAGES
FFFF
C000
8000
4000
0000
PAGE 0
FS3
FS2
FS1
FS0
PAGE 1
FS5
FS4
FS0
FS1
PROGRAM SPACE
PAGE 2
FS7
FS6
FS0
FS1
NOTHING MAPPED
PAGE 3
FS0
FS1
DATA SPACE
NOTHING MAPPED
SYSTEM RAM & I/O
PAGE X
EES3
EES2
EES1
EES0
FFFF
C000
8000
4000
1000
0000
AI03303