AN1154 STMicroelectronics, AN1154 Datasheet - Page 7

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

Matching the Functions to a M8813F1x
The mapping of the functional areas, of the original design, into the M8813F1x are shown in Table 1.
The 80C31, running at 16 MHz, has a t
An M8813F1x-15 (the 150 ns part) was selected to meet the 80C31 access time requirement.
Table 1. Discrete Solution Compared to the M8813F1x Solution
Paging/Segmentation,
PLD/Control/Demux
Supervisory/JTAG
Functional Area
and Control
Memory
Memory
I/O
Various registers used to hold data
Automatic switch to battery backup
selects to the Flash and EEPROM
or control information to be used
Design Example with Discrete
Latched data inputs and outputs
Combinatorial outputs on CPLD
Extra logic to drive the address
lines, output enables, and chip
Limited JTAG interface with no
available, and no JTAG ISP of
multiplexing of the JTAG port
Address latch logic in CPLD
128 KByte Flash Memory
Decoder (EPM7064S)
32 KByte EEPROM
by external devices
memory available
2 KByte SRAM
Components
on CPLD
AVIV
(time between address valid and instruction valid) of 207 ns.
multiplexed with other I/O, and the memory and logic
Utilizes standard JTAG and non-standard extensions
Use one Output Micro
Built-in comparator automatically switches to battery
PSD page register, PSD VM register, and prioritized
Automatically taken care of internally by the DPLD,
power when the system voltage drops below the
(to speed programming); the JTAG port can be
Port A in latched address mode (A7-A0)
within the PSD is ISP via the JTAG port.
The Matching M8813F1x Function
battery voltage on pin PC2 (V
AN1154 - APPLICATION NOTE
Use DPLD (Decoding PLD)
MCU I/O mode feature
memory access.
Same
Same
Same
same
Cell per bit for each register
STBY
)
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