AN1154 STMicroelectronics, AN1154 Datasheet - Page 77

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

INTRODUCTION
A system memory map was developed for this tutorial to take full advantage of the memory available in
the M8813F1x, and to expand beyond the 64 KByte address space limitation of the 8031 MCU. This
memory map facilitates the downloading of firmware from a host computer to the Flash memory in the PSD
using the 8031 UART. The 8031 boots from the PSD EEPROM, concurrently downloads to PSD Flash
memory, and then 8031 execution jumps from EEPROM to Flash memory. After this jump, the EEPROM
in the boot area address space is replaced with Flash memory by a special register within the PSD (the
VM Register). After that, the entire Flash memory is available to the 8031.
This system memory map also allows the concurrent downloading of boot code into the PSD EEPROM
while executing code out of PSD Flash memory. This is not possible in non-PSD systems that use PROM
for boot code.
The total memory available to the 8031 as defined in this system is:
SYSTEM MEMORY MAP
The system memory map is shown in Figure 62, Figure 63, Figure 64, and Figure 65. The labels FSx and
EESx are the names of internal memory segments within the M8813F1x device. FSx represents 16 Kbyte
Flash segments, EESx represents 8 Kbyte EEPROM segments.
In this design, paging is used because the system contains more memory than the 8031 can address
linearly. The M8813F1x facilitates paging by using a page register, which the 8031 can access. Because
paging is used, a common memory area is needed for firmware routines that must be accessible
regardless of what page the MCU is executing from. This common area resides in the lower half of each
memory page in program space (shown in Figure 62, Figure 63, Figure 64, and Figure 65). It should
contain routines that handle initialization, interrupts, implement page switching, and drive physical
devices. It is also used to keep critical data space items available at all times. For example, in this design,
the PSD control registers, I/O, and system SRAM for the stack and global variables are available on any
memory page (see Figure 62, Figure 63, Figure 64, and Figure 65).
There are two fundamental modes of operation: one is boot/download mode, and the other is normal
operation. Figure 62, Figure 63, Figure 64, and Figure 65 show the memory map during the transition from
boot/download mode to normal operation mode.
Figure 16 represents the memory map at power-on (boot). The system boots up from EEPROM, and then
facilitate a download to the main Flash memory (if needed) using the 8031 UART. At this point, all of the
PSD Flash memory is in the 8031 “data space” and all of the EEPROM is in the 8031 “program space”.
This is due to the “MCU Bus Configuration” that was performed in step 2 of the section entitled “PSDsoft
Configuration” (on page 20), and shown in Figure 16. This step of the configuration automatically sets the
VM register to 12h. Please refer to the M88 FLASH+PSD Data Sheet for information on the VM register
settings.
It is very important to note that the PSD Configuration utility initialises the VM register (located in the
CSIOP space at offset E2h), and that it can only be changed by the MCU after it has booted. After the
Flash has been programmed or validated, the Flash memory is moved from the 8031 data space to the
128 KBytes Flash
16 KBytes EEPROM for boot code
16 KBytes EEPROM for data storage
2 KBytes battery-backed SRAM (in addition to the 256 bytes SRAM resident on the 8031)
APPENDIX F: SYSTEM MEMORY MAP AND UART ISP
AN1154 - APPLICATION NOTE
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