AN1154 STMicroelectronics, AN1154 Datasheet - Page 8

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

AN1154 - APPLICATION NOTE
THE M88 FLASH+PSD FUNCTIONAL BLOCKS
The M88x3Fxx provides five system-level functional blocks, and allows the user to define and configure
these blocks to meet the design specification.
MCU Bus Interface
The MCU Bus Interface adapts the address, data, and control lines of a particular MCU to the PSD.
Choices include multiplexed or non-multiplexed address/data bus, and the associated control/handshake
signals.
PLDs (Decode for memory and registers, General logic)
The DPLD generates internal chip selects for the M88 FLASH+PSD Flash memory, EEPROM, SRAM,
Control registers and I/O Ports, Peripheral I/O mode, and Micro Cells.
The CPLD implements general logical functions, such as state machines, shift registers, counters, and
combinatorial logic.
Both PLDs are based on Flash memory technology.
I/O Ports
The M88x3Fxx has four I/O ports: Ports A, B, C, and D. These ports have several modes of operation and
may be selected within PSDsoft during design entry, or by MCU firmware at run-time. Modes that are
defined by PSDsoft are implemented with Non-Volatile Memory (NVM) configuration bits that cannot be
altered unless the device is reprogrammed. The remaining available I/O port operational modes are
determined by the MCU writing to PSD control registers. Please see Application Note AN1x55 for more
details.
Memory
The M8813F1x has 128 KBytes of Flash memory, 32 KBytes of EEPROM, and 2 KBytes of battery-backed
SRAM. All of these memories may operate concurrently. That is to say that, while one (or more) type of
memory is being written to, erased or read, the MCU can still be fetching program code from another.
These memory blocks are placed in the system address space using the PSDsoft development software.
The M88 FLASH+PSD also offers some run-time features that can be used to alter the system memory
map on the fly, which is useful for memory paging, and ISP.
JTAG ISC interface
The M88 FLASH+PSD family includes a JTAG channel for In-System Programming (ISP). This ISP
function is an extension of the typical JTAG boundary-scan function. It is an implementation of the JTAG-
ISC (In-System Configuration) specification that is becoming an industry standard. The entire PSD device
may be configured and programmed while soldered to the end product. The PSD can be completely blank
before programming because the JTAG interface needs no assistance from the MCU. ST has enhanced
the standard four-wire IEEE 1149.1 JTAG interface by making available two additional handshake lines to
speed the programming.
The use of the JTAG interface, and the two additional handshake lines, are defined using PSDsoft. Also,
the MCU has some control over the JTAG interface at run-time.
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